Electronics assemblies employing copper in multiple locations
Electronic assemblies may be fabricated with interconnects of different types present in multiple locations and comprising fused copper nanoparticles. Each interconnect or a portion thereof comprises a bulk copper matrix formed from fusion of copper nanoparticles or a reaction product formed from copper nanoparticles. The interconnects may comprise a copper-based wire bonding assembly, a copper-based flip chip connection, a copper-based hermetic seal assembly, a copper-based connector between an IC substrate and a package substrate, a copper-based component interconnect, a copper-based interconnect comprising via copper for establishing electrical communication between opposite faces of a package substrate, a copper-based interconnect defining a heat channel formed from via copper, and any combination thereof.
1. An electronic assembly comprising:
an IC substrate;
a package substrate; and
a plurality of interconnects in direct or indirect contact with at least the IC substrate;
wherein each interconnect comprises a bulk copper matrix formed from fusion of copper nanoparticles or a reaction product formed from copper nanoparticles; and
wherein the bulk copper matrix has a nanoporosity of 2-15% and a pore size of about 50 nm to about 500 nm.
2. The electronic assembly of claim 1 , wherein there are no interconnects of any type lacking copper in direct or indirect contact with at least the IC substrate.
3. The electronic assembly of claim 1 , wherein the plurality of interconnects comprises a first plurality of interconnects disposed between the IC substrate and the package substrate.
4. The electronic assembly of claim 3 , wherein the first plurality of interconnects are spherical or cylindrical in shape.
5. The electronic assembly of claim 3 , wherein a plurality of under bump metallization contacts are disposed on the IC substrate and a plurality of copper pads are disposed on the package substrate, and each of the first plurality of interconnects is disposed between a corresponding under bump metallization contact and a corresponding copper pad.
6. The electronic assembly of claim 5 , wherein the plurality of under bump metallization contacts are separated from one another by a first passivation/solder resist layer and the plurality of copper pads are separated from one another by a second passivation/solder resist layer.
7. The electronic assembly of claim 3 , further comprising:
a flip chip disposed upon the IC substrate;
wherein the plurality of interconnects further comprises a second plurality of interconnects between the flip chip and the IC substrate.
8. The electronic assembly of claim 7 , wherein the second plurality of interconnects are spherical or cylindrical in shape.
9. The electronic assembly of claim 7 , wherein a plurality of under bump metallization contacts are disposed on the flip chip and a plurality of copper pads are disposed on the IC substrate, and each of the second plurality of interconnects is disposed between a corresponding under bump metallization contact and a corresponding copper pad.
10. The electronic assembly of claim 9 , wherein the plurality of under bump metallization contacts are separated from one another by a first passivation/solder resist layer and the plurality of copper pads are separated from one another by a second passivation/solder resist layer.
11. The electronic assembly of claim 3 , further comprising:
a flip chip disposed upon the IC substrate;
wherein at least a portion of the plurality of interconnects are between the flip chip and the IC substrate.
12. The electronic assembly of claim 11 , wherein the plurality of interconnects are spherical or cylindrical in shape.
13. The electronic assembly of claim 11 , wherein a plurality of under bump metallization contacts are disposed on the flip chip and a plurality of copper pads are disposed on the IC substrate, and each of the plurality of interconnects between the flip chip and the IC substrate is disposed between a corresponding under bump metallization contact and a corresponding copper pad.
14. The electronic assembly of claim 13 , wherein the plurality of under bump metallization contacts are separated from one another by a first passivation/solder resist layer and the plurality of copper pads are separated from one another by a second passivation/solder resist layer.
15. The electronic assembly of claim 1 , wherein the bulk copper matrix comprises at least 90% dense bulk copper metal.
16. The electronic assembly of claim 1 , wherein the bulk copper matrix further comprises a grain growth inhibitor.
17. The electronic assembly of claim 1 , wherein the plurality of interconnects have a pitch above about 1 μm.
18. The electronic assembly of claim 17 , wherein the pitch ranges from about 1 μm to about 10 μm in size.