Standalone high voltage galvanic isolation capacitors
A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.
1. A multi-chip module (MCM) comprising:
a first die having a first integrated circuit configured to operate at a first voltage level;
a second die having a second integrated circuit configured to operate at a second voltage level, a difference between the first voltage level and the second voltage level being greater than about 500 V; and
a third die containing a first capacitor coupled in series with a second capacitor through a lower metal plate, the first capacitor including a first upper metal plate having a first area, the first upper metal plate being coupled to the first integrated circuit, the second capacitor including a second upper metal plate having a second area, the second upper metal plate being coupled to the second integrated circuit, a ratio of the first area to the second area being 5.0 or greater.
2. The MCM as recited in claim 1 in which the first die and the third die are mounted to a first die attach pad (DAP) and the second die is mounted to a second DAP that is conductively isolated from the first DAP.
3. The MCM as recited in claim 1 in which the third die includes:
a semiconductor substrate;
a pre-metal dielectric (PMD) layer over the semiconductor substrate, the PMD layer having a first thickness;
the lower metal plate in contact with the PMD layer;
an inter-level dielectric (ILD) layer on the lower metal plate, the ILD layer having a second thickness, a ratio of the first thickness to the second thickness being between about 1 and about 1.55; and
the first upper metal plate and the second upper metal plate being in contact with the ILD layer.
4. The MCM as recited in claim 3 in which the PMD layer includes:
a first oxide layer over the semiconductor substrate;
a first nitrogen-containing dielectric layer over the first oxide layer and in contact with the lower metal plate.
5. The MCM as recited in claim 3 in which the ILD layer includes:
a second oxide layer over the lower metal plate;
a second nitrogen-containing dielectric layer over the second oxide layer and in contact with the first upper metal plate and the second upper metal plate.
6. The MCM as recited in claim 1 in which the lower metal plate includes a capacitance-reducing opening, the capacitance-reducing opening in a location under the second upper metal plate.
7. The MCM as recited in claim 6 in which the capacitance-reducing opening includes a trench that isolates a portion of the lower metal plate from a remainder of the lower metal plate.
8. The MCM as recited in claim 6 in which the capacitance-reducing opening includes a circular opening through the lower metal plate.
9. The MCM as recited in claim 1 in which the lower metal plate, the first upper metal plate, and the second upper metal plate comprise aluminum.
10. A method of forming a multi-chip module (MCM) comprising:
mounting a first die to a first die attach pad (DAP), the first die having a first integrated circuit configured to operate at a first voltage level;
mounting a second die to a second DAP, the second die having a second integrated circuit configured to operate at a second voltage level, a difference between the first voltage level and the second voltage level being greater than about 500 V; and
mounting a third die to a third DAP, the third die containing a first capacitor coupled in series with a second capacitor through a lower metal plate, the first capacitor including a first upper metal plate having a first area, the first upper metal plate being coupled to the first integrated circuit, the second capacitor including a second upper metal plate having a second area, the second upper metal plate being coupled to the second integrated circuit, a ratio of the first area to the second area being 5.0 or greater.
11. The method as recited in claim 10 in which the first DAP is conductively isolated from the second DAP.
12. The method as recited in claim 10 in which the third die includes:
a semiconductor substrate;
a pre-metal dielectric (PMD) layer on the semiconductor substrate, the PMD layer having a first thickness;
the lower metal plate in contact with the PMD layer;
an inter-level dielectric (ILD) layer on the lower metal plate, the ILD layer having a second thickness, a ratio of the first thickness to the second thickness being between about 1 and about 1.55; and
the first upper metal plate and the second upper metal plate being in contact with the ILD layer.
13. The method as recited in claim 12 in which the PMD layer includes:
a first oxide layer over the semiconductor substrate;
a first nitrogen-containing dielectric layer over the first oxide layer and in contact with the lower metal plate.
14. The method as recited in claim 12 in which the ILD layer includes:
a second oxide layer over the lower metal plate;
a second nitrogen-containing dielectric layer over the second oxide layer and in contact with the first upper metal plate and the second upper metal plate.
15. The method as recited in claim 10 in which the lower metal plate includes a capacitance-reducing opening, the capacitance-reducing opening in a location under the second upper metal plate.
16. The method as recited in claim 15 in which the capacitance-reducing opening includes a trench that isolates a portion of the lower metal plate from a remainder of the lower metal plate.
17. The method as recited in claim 15 in which the capacitance-reducing opening includes a circular opening through the lower metal plate.
18. The method as recited in claim 10 in which the lower metal plate, the first upper metal plate, and the second upper metal plate comprise aluminum.