Low power comparator
A comparator is presented. The comparator includes an input port for receiving an input voltage; an output port for providing an output voltage; a resistive divider, first and second transistors, and a differential amplifier. The resistive divider has a first node for providing a first voltage and a second node for providing a second voltage. The first transistor has a control terminal coupled to the first node, a first terminal coupled to the input port, and a second terminal coupled to a common node. The second transistor has a control terminal coupled to the second node, a first terminal coupled to the input port, and a second terminal coupled to the common node. The differential amplifier has a first input coupled to the first terminal of the first transistor, a second input coupled to the first terminal of the second transistor and an output coupled to the output port.
1. A comparator comprising:
an input port for receiving an input voltage;
an output port for providing an output voltage;
a resistive divider having a first node for providing a first voltage and a second node for providing a second voltage;
a first transistor having a control terminal coupled to the first node, a first terminal coupled to the input port, and a second terminal coupled to a common node;
a second transistor having a control terminal coupled to the second node, a first terminal coupled to the input port, and a second terminal coupled to the common node; and
a differential amplifier having a first input coupled to the first terminal of the first transistor, a second input coupled to the first terminal of the second transistor and an output coupled to the output port,
wherein the first transistor is coupled to the input port via a third transistor, and wherein the second transistor is coupled to the input port via a fourth transistor,
wherein the third transistor has a control terminal coupled to the first input of the differential amplifier, and wherein the fourth transistor has a control terminal coupled to the second input of the differential amplifier, and
wherein the first transistor is an anti-doped gate transistor in which the gate of the first transistor is doped with a doping type opposite to that of the first transistor type, and wherein the second transistor is a normal gate transistor in which the gate of the second transistor is doped with a same doping type as the second transistor type.
2. The comparator as claimed in claim 1 ,
wherein the first transistor has a first threshold voltage and the second transistor has a second threshold voltage, and
wherein the first threshold voltage is greater than the second threshold voltage.
3. The comparator as claimed in claim 1 ,
wherein the comparator has a temperature compensated threshold voltage.
4. The comparator as claimed in claim 3 ,
wherein the first transistor has a first size and the second transistor has a second size, and
wherein a size ratio of the first size over the second size is selected to achieve the temperature compensated threshold voltage.
5. The comparator as claimed in claim 1 ,
wherein the first and second transistors are n-type transistors.
6. The comparator as claimed in claim 1 ,
wherein the third and fourth transistors are p-type transistors.
7. The comparator as claimed in claim 1 ,
wherein the third and fourth transistors are diode-connected transistors.
8. The comparator as claimed in claim 1 , comprising a hysteresis switch having a control terminal coupled to the output port.
9. An electronic device comprising the comparator as claimed in claim 1 .
10. The electronic device as claimed in claim 9 ,
wherein the electronic device is a power supply, and
wherein the comparator is implemented in a feedback loop of the power supply.
11. The electronic device as claimed in claim 9 ,
wherein the electronic device is a charger comprising a supervisor circuit configured to identify at least one of an under voltage and an over voltage, and
wherein the supervisor circuit comprises one or more of the comparator.
12. A method of comparing voltages, the method comprising
receiving an input voltage at an input port;
dividing the input voltage with a resistive divider to provide a first voltage at a first node and a second voltage at a second node;
providing a first transistor having a control terminal coupled to the first node, a first terminal coupled to the input port, and a second terminal coupled to a common node;
providing a second transistor having a control terminal coupled to the second node, a first terminal coupled to the input port, and a second terminal coupled to the common node;
providing a differential amplifier having a first input coupled to the first terminal of the first transistor, a second input coupled to the first terminal of the second transistor; and
generating a difference voltage using the differential amplifier,
wherein the first transistor is coupled to the input port via a third transistor, and wherein the second transistor is coupled to the input port via a fourth transistor,
wherein the third transistor has a control terminal coupled to the first input of the differential amplifier, and wherein the fourth transistor has a control terminal coupled to the second input of the differential amplifier, and
wherein the first transistor is an anti-doped gate transistor in which the gate of the first transistor is doped with a doping type opposite to that of the first transistor type, and wherein the second transistor is a normal gate transistor in which the gate of the second transistor is doped with a same doping type as the second transistor type.
13. The method as claimed in claim 12 , comprising
converting the first voltage into a first current using the first transistor; and
converting the second voltage into a second current using the second transistor.
14. The method as claimed in claim 13 , comprising generating a bias current by adding the first current and the second current.
15. The method as claimed in claim 12 , comprising generating a comparator threshold voltage based on a difference between the first voltage and the second voltage.
16. The method as claimed in claim 12 , wherein the first transistor has a first size and second transistors has a second size, the method further comprising selecting a size ratio of the first size over the second size to obtain a temperature compensated comparator threshold voltage.