Auto-focus engine architecture for image signal processor
Embodiments relate to image signal processors (ISP) that include binner circuits that down-sample an input image. An input image may include a plurality of pixels. The output image of the binner circuit may include a reduced number of pixels. The binner circuit may include a plurality of different operation modes. In a bin mode, the binner circuit may blend a subset of input pixel values to generate an output pixel quad. In a skip mode, the binner circuit may select one of the input pixel values as the output pixel pixel. The selection may be performed randomly to avoid aliasing. In a luminance mode, the binner circuit may take a weighted average of a subset of pixel values having different colors. In a color value mode, the binner circuit may select one of the colors in a subset of pixel values as an output pixel value.
1. An auto-focus circuit, comprising:
a patterned defect pixel (PDP) processing circuit configured to:
identify one or more focus pixels in raw image data captured by an image sensor; and
process the one or more focus pixels to increase a color value of the one or more focus pixels relative to color values of other pixels in the raw image data;
a gain offset clamp (GOC) circuit coupled to the PDP processing circuit and configured to perform a black level compensation for a color component in the raw image data; and
an auto-focus engine (AFE) circuit coupled to the GOC circuit and the PDP processing circuit and configured to:
receive a version of the raw image data after being processed by the GOC circuit and the PDP processing circuit; and
generate a focus signal for the image sensor to cause a change of a lens position for the image sensor based on the received version of the raw image data.
2. The auto-focus circuit of claim 1 , wherein the PDP processing circuit is directly coupled to the image sensor and configured to receive the raw image data captured by the image sensor.
3. The auto-focus circuit of claim 1 , further comprising:
a crop circuit coupled to the image sensor and the PDP processing circuit and configured to:
receive the raw image data captured by the image sensor;
reduce a size of the raw image data by cropping the raw image data to generate cropped raw image data; and
provide the cropped raw image data to the PDP processing circuit.
4. The auto-focus circuit of claim 3 , wherein the crop circuit is configured to operate in one or more of operational modes selected from a first mode to enable selective processing of portions of the raw image data, a second mode to start the cropping of the raw image data by starting at a location and continuing in a horizontal direction or in a vertical direction, and a third mode to crop the raw image data based on a frame width or a frame height of a plurality of pixels.
5. The auto-focus circuit of claim 1 , wherein a location of the one or more focus pixels is predetermined by a placement of the one or more focus pixels in an image sensor pixel array.
6. The auto-focus circuit of claim 1 , wherein the one or more focus pixels have lower color values compared to the other pixels of the raw image data.
7. The auto-focus circuit of claim 1 , wherein the GOC circuit is configured to perform linear transformation operations on the raw image data of an input image captured by the image sensor to remove an offset effect performed on the input image.
8. The auto-focus circuit of claim 1 , wherein the AFE circuit is configured to:
perform pixel corrections on the one or more focus pixels on the received version of the raw image data;
determine a phase shift among the one or more focus pixels after the pixel corrections have been performed based on a difference between corrected one or more focus pixels and the one or more focus pixels before being corrected; and
generate the focus signal for the image sensor based on the phase shift.
9. The auto-focus circuit of claim 1 , wherein the AFE circuit is configured to:
select a first focus pixel value that corresponds to a first focus pixel with a first portion blocked from light exposure;
calculate a first corrected focus pixel value that estimates the first focus pixel value in response to the first portion not being blocked;
select a second focus pixel value that corresponds to a second focus pixel with a second portion blocked from the light exposure;
calculate a second corrected focus pixel value that estimates the second focus pixel value in response to the second portion not being blocked;
determine a phase shift from a difference between the first and the second corrected focus pixel values; and
generate the focus signal for the image sensor based on the phase shift.
10. The auto-focus circuit of claim 1 , further comprising:
a subsample binner (SBIN) circuit coupled to the AFE circuit to perform down-sample operations on the raw image data to reduce a pixel rate of the raw image data.
11. The auto-focus circuit of claim 10 , further comprising:
a statistics circuit coupled to the SBIN circuit to generate statistics on a version of an output image of the SBIN circuit.
12. The auto-focus circuit of claim 11 , wherein the statistics circuit comprises a radial vignetting correction (RVC) circuit, a histogram (HIST) generation circuit, and a min max sum (MMS) circuit.
13. A method, comprising:
identifying, by a patterned defect pixels (PDP) processing circuit of an auto-focus circuit, one or more focus pixels in raw image data captured by an image sensor;
processing, by the PDP processing circuit, the one or more focus pixels to increase a color value of the one or more focus pixels relative to color values of other pixels in the raw image data;
performing, by a gain offset clamp (GOC) circuit of the auto-focus circuit, a black level compensation for a color component in the raw image data; and
generating, by an auto-focus engine (AFE) circuit of the auto-focus circuit, a focus signal for the image sensor to cause a change of a lens position for the image sensor based on a version of the raw image data after processing the one or more focus pixels and performing the black level compensation.
14. The method of claim 13 , further comprising:
receiving, by a crop circuit of the auto-focus circuit, the raw image data captured by the image sensor;
reducing, by the crop circuit, a size of the raw image data by cropping the raw image data; and
providing, by the crop circuit, the cropped raw image data to the PDP processing circuit.
15. The method of claim 13 , wherein the one or more focus pixels have lower color values compared to the other pixels of the raw image data.
16. A system, comprising:
an image sensor configured to capture raw image data; and
an auto-focus circuit coupled to the image sensor, comprising:
a patterned defect pixels (PDP) processing circuit configured to:
identify one or more focus pixels in the raw image data captured by the image sensor; and
process the one or more focus pixels to increase a color value of the one or more focus pixels relative to color values of other pixels of the raw image data; and
an auto-focus engine (AFE) circuit coupled to the PDP processing circuit and configured to:
receive a version of the raw image data after being processed by the PDP processing circuit; and
generate a focus signal for the image sensor to cause a change of a lens position for the image sensor based on the received version of the raw image data.
17. The system of claim 16 , wherein the auto-focus circuit further comprises:
a crop circuit coupled to the image sensor and the PDP processing circuit and configured to:
receive the raw image data captured by the image sensor;
reduce a size of the raw image data by cropping the raw image data; and
provide the cropped raw image data to the PDP processing circuit.
18. The system of claim 16 , wherein the auto-focus circuit further comprises:
a subsample binner (SBIN) circuit coupled to the AFE circuit to perform down-sample operations on the raw image data to reduce a pixel rate of the raw image data.
19. The system of claim 18 , wherein the auto-focus circuit further comprises:
a statistics circuit coupled to the SBIN circuit to generate statistics on a version of an output image of the SBIN circuit.
20. The system of claim 19 , wherein the statistics circuit comprises a radial vignetting correction (RVC) circuit, a histogram (HIST) generation circuit, and a min max sum (MMS) circuit.