IP Library › Granted Patent US 12,232,257
Granted Patent B2
US 12,232,257 · App. 17/456,390 · Granted Feb 18, 2025

Wiring substrate

Inventors: Shunsuke Sakai (Ogaki, JP); Shuto Iwata (Ogaki, JP); Ikuya Terauchi (Ogaki, JP); Takahiro Yamada (Ogaki, JP)
Assignee: IBIDEN CO., LTD.
H05K1/111H05K1/116H05K1/18H05K2201/096H05K2201/09609
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Quick Facts
Patent No.
US 12,232,257
App. No.
17/456,390
Granted
Feb 18, 2025
Kind
B2
Abstract

A wiring substrate includes an insulating layer, a conductor layer formed on the insulating layer and including a conductor pad having a rectangular planar shape, and a solder resist layer formed on the insulating layer such that the solder resist layer is covering the conductor layer formed on the insulating layer. The solder resist layer has an opening formed such that the opening is exposing 50% or more of an area of a surface of the conductor pad on the opposite side with respect to the insulating layer and exposing a side surface and the surface of the conductor pad at side portions of a peripheral edge of the conductor pad and that the solder resist layer is covering the side surface and the surface of the conductor pad at one or more of corner portions of the peripheral edge of the conductor pad.

Claims (30)

1. A wiring substrate, comprising:

an insulating layer;

a conductor layer formed on the insulating layer and including a conductor pad having a rectangular planar shape; and

a solder resist layer formed on the insulating layer such that the solder resist layer is covering the conductor layer formed on the insulating layer,

wherein the solder resist layer has an opening formed such that the opening is exposing 50% or more of an area of a surface of the conductor pad on an opposite side with respect to the insulating layer and that a side surface of the conductor pad and the surface of the conductor pad are entirely exposed except the side surface and surface of the conductor pad at at least one of corner portions of a peripheral edge of the conductor pad, and the solder resist layer is formed such that the solder resist layer has at least one covering portion covering the at least one of the corner portions of the conductor pad and that each of the corner portions has a curved outer edge.

2. The wiring substrate according to claim 1 , wherein the solder resist layer is formed such that the solder resist layer is covering all of the corner portions of the peripheral edge of the conductor pad.

3. The wiring substrate according to claim 2 , wherein the solder resist layer is formed such that the solder resist layer has the covering portions having outer edges covering the corner portions of the conductor pad respectively along outer edges of the corner portions of the conductor pad.

4. The wiring substrate according to claim 2 , further comprising:

a surface treatment layer covering the conductor pad.

5. The wiring substrate according to claim 2 , wherein the wiring substrate has a first surface side and a second surface side on an opposite side with respect to the first surface side such that the wiring substrate has a component mounting surface configured to mount a component thereon on the first surface side and that the conductor layer is formed on a second surface side.

6. The wiring substrate according to claim 5 , wherein the conductor layer is formed such that the conductor pad is configured to be connected to an external element.

7. The wiring substrate according to claim 5 , further comprising:

a plurality of component mounting pads formed on the component mounting surface such that the conductor pad of the conductor layer is larger than each of the component mounting pads.

8. The wiring substrate according to claim 7 , further comprising:

a second solder resist layer formed on the component mounting surface and having a plurality of openings such that the second solder resist layer is covering peripheral edges of the component mounting pads, and that portions other than the peripheral edges of the component mounting pads are exposed in the openings of the second solder resist layer.

9. The wiring substrate according to claim 5 , wherein the insulating layer includes a core material.

10. The wiring substrate according to claim 2 , wherein the solder resist is formed such that the opening has a periphery that is substantially parallel to the periphery of the conductor pad at side portions of the conductor pad.

11. The wiring substrate according to claim 2 , wherein the conductor layer is formed such that the corner portions of the conductor pad are R-chamfered.

12. The wiring substrate according to claim 1 , further comprising:

a surface treatment layer covering the conductor pad.

13. The wiring substrate according to claim 12 , wherein the wiring substrate has a first surface side and a second surface side on an opposite side with respect to the first surface side such that the wiring substrate has a component mounting surface configured to mount a component thereon on the first surface side and that the conductor layer is formed on a second surface side.

14. The wiring substrate according to claim 1 , wherein the wiring substrate has a first surface side and a second surface side on an opposite side with respect to the first surface side such that the wiring substrate has a component mounting surface configured to mount a component thereon on the first surface side and that the conductor layer is formed on a second surface side.

15. The wiring substrate according to claim 14 , wherein the conductor layer is formed such that the conductor pad is configured to be connected to an external element.

16. The wiring substrate according to claim 14 , further comprising:

a plurality of component mounting pads formed on the component mounting surface such that the conductor pad of the conductor layer is larger than each of the component mounting pads.

17. The wiring substrate according to claim 16 , further comprising:

a second solder resist layer formed on the component mounting surface and having a plurality of openings such that the second solder resist layer is covering peripheral edges of the component mounting pads, and that portions other than the peripheral edges of the component mounting pads are exposed in the openings of the second solder resist layer.

18. The wiring substrate according to claim 1 , wherein the insulating layer includes a core material.

19. The wiring substrate according to claim 1 , wherein the conductor layer is formed such that the corner portions of the conductor pad are R-chamfered.

20. The wiring substrate according to claim 1 , wherein the solder resist is formed such that the opening has a periphery that is substantially parallel to the periphery of the conductor pad at side portions of the conductor pad.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 24, 2021
From: SAKAI, SHUNSUKE; IWATA, SHUTO; TERAUCHI, IKUYA; YAMADA, TAKAHIRO
To: IBIDEN CO., LTD.
Reel/Frame 058202/0773 →
Priority Claims (1)
JP 2020-207761 · Dec 15, 2020 · national
Continuity (1)
Related Publication 20220192018A1 · Jun 16, 2022
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