Apparatuses and methods for timing skew calibration
An apparatus and method for timing skew calibration. For example, the apparatus may include an analog-to-digital conversion circuit configured to sample an input signal based on a clock signal and convert the sampled input signal into a digital code, a skew detection circuit configured to calculate a first sum of standard deviations for respective levels of the digital code, compare the first sum of the standard deviations with a previously calculated second sum of standard deviations, and select a smaller value from among the first sum and the second sum, and a compensation circuit configured to compensate for a skew of the clock signal based on the selected one of the first sum and the second sum.
1. An apparatus comprising:
an analog-to-digital conversion circuit configured to sample an input signal based on a clock signal and configured to convert the sampled input signal into a digital code;
a skew detection circuit configured to receive the digital code from the analog-to-digital conversion circuit, calculate a first sum of standard deviations for respective levels of the digital code, compare the first sum of the standard deviations with a previously calculated second sum of standard deviations, and select a smaller value from among the first sum and the second sum; and
a compensation circuit configured to compensate for a skew of the clock signal based on the selected smaller value from among the first sum and the second sum.
2. The apparatus of claim 1 , wherein the compensation circuit is further configured to compensate for the skew by delaying the clock signal.
3. The apparatus of claim 1 , wherein the compensation circuit is further configured to compensate for the skew by performing interpolation with respect to the clock signal.
4. The apparatus of claim 1 , further comprising:
a multiplexer configured to receive the digital code from the analog-to-digital conversion circuit and serialize the digital code; and
a slicer configured to receive the serialized digital code from the multiplexer, divide the serialized digital code by levels, and transmit a level-divided digital code to the skew detection circuit.
5. The apparatus of claim 1 , wherein the analog-to-digital conversion circuit comprises a plurality of analog-to-digital converters (ADCs), and
wherein each of the plurality of ADCs is connected to a respective slicer.
6. The apparatus of claim 5 , wherein the slicers to which the plurality of ADCs are respectively connected are configured to receive a digital code from the respective one of the plurality of ADCs, divide the received digital code by levels, and transmit a level-divided digital code to the skew detection circuit.
7. The apparatus of claim 1 , wherein the skew detection circuit is further configured to compare the first sum of standard deviations for respective levels of the digital code with a previously calculated third sum of standard deviations and select a smallest value from among the first sum, second sum, and third sum.
8. An apparatus comprising:
an analog-to-digital conversion circuit configured to sample an input signal based on a clock signal and convert the sampled input signal into a digital code;
a skew detection circuit configured to receive the digital code from the analog-to-digital conversion circuit, calculate a first sum of variances for respective levels of the digital code, compare the first sum of the variances with a previously calculated second sum of variances, and select a smaller value from among the first sum and the second sum; and
a compensation circuit configured to compensate for a skew of the clock signal based on a selected smaller value from among the first sum and the second sum.
9. The apparatus of claim 8 , wherein the compensation circuit is further configured to compensate for the skew by delaying the clock signal.
10. The apparatus of claim 8 , wherein the compensation circuit is further configured to compensate for the skew by performing interpolation with respect to the clock signal.
11. The apparatus of claim 8 , further comprising:
a multiplexer configured to receive the digital code from the analog-to-digital conversion circuit and serialize the digital code; and
a slicer configured to receive the serialized digital code from the multiplexer, divide the serialized digital code by levels, and transmit a level-divided digital code to the skew detection circuit.
12. The apparatus of claim 8 , wherein the analog-to-digital conversion circuit comprises a plurality of analog-to-digital converters (ADCs), and
wherein each of the plurality of ADCs is connected to a respective slicer.
13. The apparatus of claim 12 , wherein the slicers to which the plurality of ADCs are respectively connected are configured to receive a digital code from the respective one of the plurality of ADCs, divide the received digital code by levels, and transmit a level-divided digital code to the skew detection circuit.
14. The apparatus of claim 8 , wherein the skew detection circuit is further configured to compare the first sum of variances for respective levels of the digital code with a previously calculated third sum of a plurality of variances and select a smallest value from among the first sum, second sum, and third sum.
15. An apparatus comprising:
a time interleaved analog-to-digital converter (TIADC) comprising at least one switch that is configured to sample an input signal based on a clock signal and one or more analog-to-digital converter (ADC) that is configured to convert the sampled input signal into a digital code;
a sigma monitor configured to calculate a first sum of standard deviations for respective levels of the digital code;
a decision logic configured to receive the sum of the standard deviations from the sigma monitor, compare the first sum of the standard deviations with a previously calculated second sum of standard deviations, and select a smaller value from among the first sum and the second sum; and
a compensation circuit configured to compensate for a skew of the clock signal based on a selected smaller value from among the first sum and the second sum.
16. The apparatus of claim 15 , wherein the compensation circuit is further configured to compensate for the skew by delaying the clock signal.
17. The apparatus of claim 15 , wherein the compensation circuit is further configured to compensate for the skew by performing interpolation with respect to the clock signal.
18. The apparatus of claim 15 , further comprising:
a multiplexer configured to receive the digital code from the TIADC and serialize the digital code; and
a slicer configured to receive the serialized digital code from the multiplexer, divide the serialized digital code by levels, and transmit a level-divided digital code to the sigma monitor.
19. The apparatus of claim 15 , wherein each of the one or more ADCs is connected to a respective slicer, and
wherein each of the slicers to which the one or more ADCs are respectively connected is configured to receive a digital code from the ADC connected respectively thereto, divide the received digital code by levels, and transmit a level-divided digital code to the sigma monitor.
20. The apparatus of claim 15 , wherein the sigma monitor is further configured to transmit the first sum of standard deviations for respective levels of the digital code and a previously calculated third sum of a plurality of standard deviations to the decision logic, and
the decision logic is further configured to select a smallest value from among the first sum, second sum, and third sum.