Frame-based, low power interfaces between devices with different I/O signals
High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.
1. A repeater comprising:
a host-side squelch detector; and
a host-side receiver and a host-side transmitter, each coupled to the host-side squelch detector, and the host-side receiver and the host-side transmitter are configured to be in an inactive state for a second time period responsive to the host-side squelch detector determining that a micro frame discludes a data packet during a first time period.
2. The repeater of claim 1 further comprising:
a peripheral-side squelch detector; and
a peripheral-side receiver and a peripheral-side transmitter, each coupled to the peripheral-side squelch detector, and the peripheral-side receiver, the peripheral-side transmitter and the peripheral-side squelch detector are configured to be in the inactive state for the second time period responsive to the host-side squelch detector determining that the micro frame discludes the data packet during the first time period.
3. The repeater of claim 2 , wherein the host-side squelch detector is configured to be in an active state after the second time period and before a next micro frame is received.
4. The repeater of claim 3 , wherein the host-side receiver and the peripheral-side transmitter are configured to be in the active state after the second time period and before the next micro frame is received.
5. The repeater of claim 4 , wherein the host-side transmitter, the peripheral-side receiver, and the peripheral-side squelch detector are configured to be in a standby state during the first time period.
6. The repeater of claim 5 , wherein the host-side transmitter, the peripheral-side receiver, and the peripheral-side squelch detector are configured to be in the standby state after the second time period and before the next micro frame is received.
7. The repeater of claim 5 , wherein the host-side squelch detector, the host-side receiver and the peripheral-side transmitter are configured to be in the active state during an initial time period before the first time period.
8. The repeater of claim 7 , wherein the host-side transmitter, the peripheral-side receiver, and the peripheral-side squelch detector are configured to be in the standby state during the initial time period before the first time period.
9. The repeater of claim 8 further comprising:
a loss of signal detector (LOS) coupled to the host-side squelch detector, and configured to be in the inactive state during the second time period; and
a disconnect detector coupled to the peripheral-side squelch detector, and configured to be in the inactive state during the second time period.
10. A circuit comprising:
a first receiver and a first transmitter;
a second transmitter coupled to the first receiver;
a second receiver coupled to the first transmitter and the second transmitter;
a first detector coupled to the first receiver and the first transmitter; and
a second detector coupled to the second receiver and the second transmitter;
wherein the first receiver, the first transmitter and the second detector are configured to be in an inactive state for a second time period responsive to the first detector determining that a micro frame discludes a data packet during a first time period.
11. The circuit of claim 10 , wherein the first receiver and the first transmitter are coupled to a USB 2.0 port, and the second receiver and the second transmitter are coupled to an eUSB2 port.
12. The circuit of claim 10 , wherein the first receiver and the first transmitter are coupled to an eUSB2 port, and the second receiver and the second transmitter are coupled to a USB 2.0 port.
13. The circuit of claim 12 , wherein the second receiver and the second transmitter are configured to be in the inactive state for the second time period responsive to the first detector determining that the micro frame discludes the data packet during the first time period.
14. The circuit of claim 13 , wherein the first detector is configured to be in an active state after the second time period and before a next micro frame is received.
15. The circuit of claim 14 , wherein the first receiver and the second transmitter are configured to be in the active state after the second time period and before the next micro frame is received.
16. The circuit of claim 15 , wherein the first transmitter, the second receiver, and the second detector are configured to be in a standby state during the first time period.
17. The circuit of claim 16 , wherein the first transmitter, the second receiver, and the second detector are configured to be in the standby state after the second time period and before the next micro frame is received.
18. A method comprising:
detecting by a first detector, during a first time period, a start of a micro frame;
determining, during a second time period after the first time period, whether at least one data packet is contained in the micro frame; and
inactivating, in response to determining that the micro frame discludes a data packet during the second time period, a first receiver, a first transmitter, a second receiver, a second transmitter and a second detector during a third time period after the second time period, the first receiver and the first transmitter are coupled to the first detector, and the second transmitter is coupled to the first receiver and the second detector, and the second receiver is coupled to the second transmitter and the second detector.
19. The method of claim 18 further comprising keeping the first detector active during the third time period.
20. The method of claim 18 further comprising activating the first receiver and the second transmitter after the third time period and before the next micro frame is received, wherein the first transmitter, the second receiver and the second detector are configured to be in a standby state after the third time period and before the next micro frame is received.