NoC routing in a multi-chip device
Embodiments herein describe a multi-chip device that includes multiple ICs with interconnected NoCs. Embodiments herein provided address translation circuitry in the ICs. The address translation circuitry establish a hierarchy where traffic originating for a first IC that is intended for a destination on a second IC is first routed to the address translation circuitry on the second IC which then performs an address translation and inserts the traffic back on the NoC in the second IC but with a destination ID corresponding to the destination. In this manner, the IC can have additional address apertures only to route traffic to the address translation circuitry of the other ICs rather than having address apertures for every destination in the other ICs.
1. A multi-chip device, comprising:
a first integrated circuit (IC) comprising a first network on a chip (NoC); and
a second IC comprising a second NoC, wherein the first and second NoCs are communicatively coupled,
wherein, when transmitting traffic from the first NoC to a local destination coupled to the second NoC in the second IC, the traffic is first routed via the first and second NoCs to address translation circuitry in the second IC, and wherein the address translation circuitry is configured to perform an address translation to identify a destination ID for the local destination, add the destination ID into the traffic, and reinsert the traffic into the second NoC to reach the local destination.
2. The multi-chip device of claim 1 , wherein the first IC includes a first NoC connection that directly couples the first NoC to a second NoC connection in the second IC coupled to the second NoC, and wherein the first and second NoC connections are disposed at peripheries of the first and second ICs.
3. The multi-chip device of claim 1 , wherein the address translation comprises using an address in the traffic received from the first IC to index into a translation table to identify the destination ID for the local destination.
4. The multi-chip device of claim 1 , wherein the first IC includes an ingress logic block that inserts the traffic into the first NoC and the second IC includes an egress logic block that receives the traffic from the second NoC and forwards the traffic to the local destination, and wherein, after receiving the traffic, the egress logic block is configured to transmit a response to the ingress logic block that is routed via the first and second NoCs without having to pass through the address translation circuitry.
5. The multi-chip device of claim 1 , wherein the first IC comprises first redistribution circuitry coupled to the first NoC and the second IC comprises second redistribution circuitry coupled to the second NoC, and
wherein the multi-chip device is configured to, when transmitting traffic from the first NoC to a local destination coupled to the second NoC in the second IC, route the traffic to the first redistribution circuitry where the traffic exits the first NoC, traverses through an inter-die connection between the first redistribution circuitry and the second redistribution circuitry, is inserted into the second NoC after reaching the second redistribution circuitry, and is forwarded by the second NoC to the local destination.
6. The multi-chip device of claim 5 , wherein the inter-die connection is at least one of a programmable logic (PL)-to-PL connection or a fabric-to-fabric connection.
7. The multi-chip device of claim 1 , further comprising:
a third IC comprising a third NoC communicatively coupled to the first and second NoCs, wherein the first, second, and third ICs are arranged in an array defining a first dimension and a second dimension that is perpendicular to the first dimension.
8. The multi-chip device of claim 7 , wherein, when routing traffic to a non-neighboring IC, the first, second, and third NoCs are configured to first route in a first dimension before routing in the second dimension to prevent deadlocks.
9. A method for routing traffic between a first integrated circuit (IC) and a second IC in a multi-chip device, comprising:
routing traffic from a first ingress logic block coupled to a first network on chip (NoC) in the first IC to address translation circuitry coupled to a second NoC in the second IC, wherein the traffic is destined to a local destination in the second IC different from the address translation circuitry;
performing, using the address translation circuitry, an address translation to identify a destination ID for the local destination of the traffic on the second IC and add the destination ID into the traffic; and
routing, using the destination ID, the traffic from a second ingress logic block of the second NoC coupled to the address translation circuitry to an egress logic block of the second NoC corresponding to the local destination.
10. The method of claim 9 , further comprising:
routing a response from the egress logic block on the second IC to the first ingress logic block on the first IC without the response passing through the address translation circuitry.
11. The method of claim 9 , wherein the first IC includes a first NoC connection that directly couples the first NoC to a second NoC connection in the second IC coupled to the second NoC, and wherein the first and second NoC connections are disposed at peripheries of the first and second ICs.
12. The method of claim 9 , wherein the address translation comprises using an address in the traffic received from the first IC to index into a translation table to identify the destination ID for the local destination.
13. The method of claim 9 , further comprising before routing the traffic to the address translation circuitry:
routing the traffic to first redistribution circuitry in the first IC where the traffic exits the first NoC; and
routing the traffic through an inter-die connection between the first redistribution circuitry and second redistribution circuitry in the second IC.
14. The method of claim 9 , wherein the multi-chip device comprises a third IC comprising a third NoC communicatively coupled to the first and second NoCs, and wherein the first, second, and third ICs are arranged in an array defining a first dimension and a second dimension that is perpendicular to the first dimension.
15. The method of claim 14 , further comprising:
routing traffic to a non-neighboring IC in the array by first routing the traffic in the first dimension before routing the traffic in the second dimension to prevent deadlocks.
16. A multi-chip device, comprising:
a first integrated circuit (IC) comprising a first network on a chip (NoC) and first redistribution circuitry; and
a second IC comprising a second NoC and second redistribution circuitry, wherein the first and second NoCs are communicatively coupled,
wherein, when transmitting traffic from the first NoC to a local destination coupled to the second NoC in the second IC, the traffic is first routed via the first NoC to the first redistribution circuitry in the first IC where the traffic exits the first NoC, traverses through an inter-die connection between the first redistribution circuitry and the second redistribution circuitry, is inserted into the second NoC after reaching the second redistribution circuitry, and is forwarded by the second NoC to the local destination, and
wherein the first IC includes a first NoC connection that directly couples the first NoC to a second NoC connection in the second IC coupled to the second NoC, wherein traffic can be transmitted between the first and second NoCs using the inter-die connection and the first and second NoC connections in parallel.
17. The multi-chip device of claim 16 , wherein the inter-die connection is at least one of a programmable logic (PL)-to-PL connection or a fabric-to-fabric connection.
18. The multi-chip device of claim 16 , wherein, when transmitting the traffic from the first NoC to the local destination coupled to the second NoC in the second IC, the traffic is first routed to address translation circuitry in the second IC, and wherein the address translation circuitry is configured to perform an address translation to identify a destination ID for the local destination.
19. The multi-chip device of claim 18 , wherein the address translation comprises using an address in the traffic received from the first IC to index into a translation table to identify the destination ID for the local destination.