Public key encryption using self powered timers
A one-time self-powered timer circuit whose state can be measured only once, after which the timer will desynchronize itself. In this manner, the timers can only be used for one-pad authentication. The security of the public-key distribution algorithms that will exploit the synchronization between billions of hardware-software timers, time reversibility of software timer and time irreversibility of hardware timers and one-time read-out to deliver classical and quantum-like benefits. System-on-chip and circuit implementation of the self-powered timer array, read-out, programming and initialization modules that implements the proposed public-key distribution algorithms.
1. A system for public key security distribution comprising:
a hardware self-powered timer; and
a server comprising a processor and a memory, the memory storing instructions that, when executed by the processor, cause the processor to:
operate as a software clone of the hardware self-powered timer, the software clone being synchronized to the hardware self-powered timer, the software clone being rewindable to any previous time-instant, and the hardware self-powered timer being time irreversible;
combine an output of the hardware self-powered timer with a pseudo-random number generator (PRNG) to produce authentication tokens;
receive a request signal from an internet-of-things (IoT) device; and
seed the PRNG using the request signal and a state of the hardware self-powered timer via a linear feedback shift register (LSFR).
2. The system of claim 1 , wherein the hardware self-powered timer desynchronizes from the software clone when the state of the hardware self-powered timer is read.
3. The system of claim 2 , wherein the state of the hardware self-powered timer is measured using a plurality of basis functions and can only be accessed through a single read-out interface once, after which the hardware self-powered timer desynchronizes into a random state.
4. The system of claim 1 , wherein the hardware self-powered timer is a Fowler-Nordheim (FN) tunneling device.
5. The system of claim 1 , wherein the system operates using hash-based mutual authentication protocol (HMAP).
6. The system of claim 1 , wherein operating a software clone of a hardware self-powered timer comprises a hash-based mutual authentication protocol (HMAP).
7. A method for public key security distribution, the method comprising:
operating a software clone of a hardware self-powered timer;
synchronizing the software clone to the hardware self-powered timer;
combining an output of the hardware self-powered timer with a pseudo-random number generator (PRNG) to produce authentication tokens;
receiving a request signal from an internet-of-things (IoT) device;
seeding the PRNG using the request signal and a state of the hardware self-powered timer via a linear feedback shift register (LSFR);
rewinding the software clone to any previous time-instant, wherein the hardware self-powered timer is time irreversible;
reading the state of the hardware self-powered timer; and
desynchronizing from the software clone.
8. The method of claim 7 , wherein reading the state of the hardware self-powered timer comprises using a plurality of basis functions and can only be accessed through a single read-out interface once, after which the hardware self-powered timer desynchronizes into a random state.
9. The method of claim 7 , wherein the hardware self-powered timer is a Fowler-Nordheim (FN) tunneling device.
10. A computing device for public key security distribution, the computing device comprising a processor and a memory, the memory containing instructions that program the processor to:
operate a software clone of a hardware self-powered timer;
synchronize the software clone to the hardware self-powered timer;
combine an output of the hardware self-powered timer with a pseudo-random number generator (PRNG) to produce authentication tokens;
receive a request signal from an internet-of-things (IoT) device;
seed the PRNG using the request signal and a state of the hardware self-powered timer via a linear feedback shift register (LSFR); and
rewind the software clone to any previous time-instant, wherein the hardware self-powered timer is time irreversible.
11. The computing device of claim 10 , wherein the memory contains instructions that program the processor to read the state of the hardware self-powered time and desynchronize from the software clone.
12. The computing device of claim 11 , wherein the memory contains instructions that program the processor to read the state of the hardware self-powered timer by using a plurality of basis functions and can only be accessed through a single read-out interface once, after which the hardware self-powered timer desynchronizes into a random state.
13. The computing device of claim 10 , wherein the memory contains instructions that program the processor to verify the public key security distribution with cyclic-redundancy-check (CRC) for error correction.
14. The computing device of claim 10 , wherein the memory contains instructions that program the processor to operate the software clone of the hardware self-powered timer using hash-based mutual authentication protocol (HMAP).