Memory system for controlling latency and method of operating the same
Provided herein may be a memory system and a method of operating the same. A memory controller may include a latency monitoring component configured to generate information about a number of occurrences of over-latency exceeding a preset reference latency among latencies each indicating a time amount required from a time point at which first command is received from an external device to a time point at which a completion response to the first command is transmitted to the external device during a first period, and a completion response controller configured to determine a first target latency based on the information about the number of occurrences of over-latency, and provide, during a second period following the first period, the external device with a completion response to a second commands provided from the external device after the first target latency has elapsed.
1. A memory controller comprising:
a latency monitoring component configured to generate information about a number of occurrences of over-latency exceeding a preset reference latency among latencies each indicating a time amount required from a time point at which first command is received from an external device to a time point at which a completion response to the first command is transmitted to the external device during a first period; and
a completion response controller configured to determine a first target latency based on the information about the number of occurrences of over-latency, and provide, during a second period following the first period, the external device with a completion response to a second command provided from the external device after the first target latency has elapsed,
wherein the information is determined using an average latency of the latencies during the first period and a maximum latency which has a largest latency among the latencies.
2. The memory controller according to claim 1 , further comprising a target latency information storage configured to store therein target latency information corresponding to the number of occurrences of over-latency, and provide the target latency information to the completion response controller.
3. The memory controller according to claim 1 , further comprising a state controller configured to provide the latency monitoring component with state information indicating that the memory device is in a sustain state when a number of free blocks included in the memory device is less than a preference value.
4. The memory controller according to claim 2 , wherein the target latency information includes a latency value increasing in proportion to the number of occurrences of over-latency.
5. The memory controller according to claim 4 ,
wherein the latency value is between the average latency and the maximum latency,
wherein the average latency is incurred to achieve average performance in a sustain state in which a number of free blocks included in the memory device is less than a reference value, and
wherein the maximum latency is incurred to achieve minimum performance required by the external device.
6. The memory controller according to claim 1 , wherein each of the first command and the second command is one of a read command and a write command.
7. The memory controller according to claim 1 , wherein the completion response controller is configured to provide the completion response to the second command immediately when an operation corresponding to the second command is completed after the first target latency has elapsed.
8. A memory system comprising:
a memory device including a plurality of memory blocks; and
a memory controller configured to delay a completion response to a second command provided from a host during a second period following a first period, based on a number of occurrences of over-latency exceeding a preset reference latency among latencies each indicating a time amount required from a time point at which a first command for the memory device is received from the host to a time point at which a completion response to the first command is provided during the first period,
wherein an amount of delay for the completion response to the second command is determined using an average latency of the latencies during the first period and a maximum latency which has a largest latency among the latencies.
9. The memory system according to claim 8 , wherein the memory controller comprises:
a target latency information storage configured to store therein target latency information corresponding to the number of occurrences of over-latency;
an operation controller configured to generate information about the number of occurrences of over-latency when a number of free blocks is less than a reference value among memory blocks included in the memory device; and
a performance controller configured to select a first target latency based on the information about the number of occurrences of over-latency and the target latency information, and delay the completion response to the second command based on the first target latency.
10. The memory system according to claim 9 , wherein the target latency information includes a latency value increasing in proportion to the number of occurrences of over-latency.
11. The memory system according to claim 10 ,
wherein the latency value is between the average latency and the maximum latency,
wherein the average latency is incurred to achieve average performance in a sustain state in which the number of free blocks is less than the reference value, and
wherein the maximum latency is incurred to achieve minimum performance required by the host.
12. The memory system according to claim 9 ,
wherein the performance controller is configured to delay the completion response to the second command by an amount corresponding to a difference between the first target latency and a completion response waiting time when the first target latency is longer than the completion response waiting time, and
wherein the completion response waiting time is from a time point at which the second command is received from the host to a time point at which the completion response to the second command is to be provided.
13. The memory system according to claim 11 , wherein the performance controller is configured to provide the completion response to the second command to the host immediately when the first target latency is shorter than a completion response waiting time that is from a time point at which the second command is received from the host to a time point at which the completion response to the second command is to be provided.
14. The memory system according to claim 8 , wherein each of the first commands and the second commands is one of a read command and a write command.
15. A method of operating a memory controller, the method comprising:
counting a number of occurrences of over-latency exceeding a preset reference latency among latencies each indicating a time amount required from a time point at which a first command is received from an external device to a time point at which a completion response to the first command is transmitted to the external device during a first period; and
delaying a completion response to a second command provided from the external device during a second period following the first period depending on a first target latency determined based on the number of occurrences of over-latency, an average latency of the latencies during the first period and a maximum latency which has a largest latency among the latencies.
16. The method according to claim 15 ,
wherein the delaying the completion responses comprises:
comparing the first target latency with a completion response waiting time; and
delaying the completion response to the second command by an amount corresponding to a difference between the first target latency and the completion response waiting time when the first target latency is longer than the completion response waiting time, and
wherein the completion response waiting time is from a time point at which the second command is received from the external device to a time point at which the completion response to the second command is to be provided.
17. The method according to claim 15 , wherein each of the first command and the second command is one of a read command and a write command.
18. The method according to claim 15 , wherein the number of occurrences of over-latency during the first period is counted when a number of free blocks included in a memory device controlled by the memory controller is less than a reference value.