Filler cell region with centrally uncut gate segments, semiconductor device including same and method of manufacturing same

1. A filler cell region in a semiconductor device, the filler cell region comprising:

gate segments extending in a first direction and being free from electrical coupling to active or passive circuitry within the filler cell region;

relative to the first direction:

a majority of first ends of the gate segments substantially aligning with a first reference line extending in a second direction perpendicular to the first direction, the first reference line being parallel and proximal to a top boundary of the filler cell region;

a majority of second ends of the gate segments substantially aligning with a second reference line extending in the second direction and being parallel and proximal to a bottom boundary of the filler cell region;

first and second ones of the gate segments extending continuously across the filler cell region; and

third & fourth and fifth & sixth ones of the gate segments being correspondingly coaxial and separated by corresponding gate-gaps located centrally in the filler cell region;

relative to the second direction, the first and second gate segments being between the third & fourth gate segments and the fifth & sixth gate segments; and

relative to the first direction:

a first end of the first gate segment extending to the top boundary; and

a second end of the second gate segment extending to the bottom boundary.

2. The filler cell region of claim 1 , wherein:

the first and second gate segments are the same.

3. The filler cell region of claim 2 , wherein:

relative to the second direction, a seventh one of the gate segments is between the third & fourth gate segments and the fifth & sixth gate segments; and

relative to the first direction:

a first end of the seventh gate segment substantially aligns with the first reference line; and

a second end of the seventh gate segment substantially aligns with the second reference line.

4. The filler cell region of claim 1 , wherein:

relative to the first direction:

a second end of the first gate segment substantially aligns with the second reference line; and

a first end of the second gate segment substantially aligns with the first reference line.

5. The filler cell region of claim 1 , further comprising:

active regions (ARs) extending in the second direction;

relative to the second direction, first & second and third & fourth ones of the ARs being correspondingly coaxial and separated by corresponding first and second AR-gaps located centrally in the filler cell region; and

wherein:

relative to the second direction:

a distance between two immediately adjacent ones of the gate segments is ≈1.0 CPP, where CPP is a unit of distance-measure;

a size of the first AR-gap, G1, between the first & second ARs is (≈1.5 CPP)≤G1; and

a size of the second AR-gap, G2, between the third & fourth ARs is (≈1.5 CPP)≤G2.

6. The filler cell region of claim 5 , wherein:

the size of the first AR-gap, G1, between the first & second ARs is (≈2.0 CPP)≤G1; and

the size of the second AR-gap, G2, between the third & fourth ARs is (≈2.0 CPP)≤G2.

7. The filler cell region of claim 6 , wherein:

the size of the first AR-gap, G1, between the first & second ARs is (≈3.0 CPP)≤G1; and

the size of the second AR-gap, G2, between the third & fourth ARs is (≈3.0 CPP)≤G2.

8. The filler cell region of claim 5 , wherein:

a configuration (A) or a configuration (B) is true;

for the configuration (A):

the first gate segment is over the first AR-gap and the second gate segment is over the second AR; and

the first gate segment is over the third AR and the second gate segment is over the second AR-gap; and

for the configuration (B):

the first gate segment is over the first AR and the second gate segment is over the first AR-gap; and

the first gate segment is over the second AR-gap and the second gate segment is over the fourth AR.

9. The filler cell region of claim 5 , wherein:

a configuration (A) or a configuration (B) is true;

for the configuration (A):

the first gate segment is over the first AR-gap; and

the second gate segment is over the second AR-gap; and

for the configuration (B):

the second gate segment is over the first AR-gap; and

the first gate segment is over the second AR-gap;

relative to the first direction, seventh & eighth and ninth & tenth ones of the gate segments are correspondingly coaxial and separated by corresponding gate-gaps located centrally in the filler cell region;

relative to the second direction, the first and second gate segments, the third & fourth gate segments and the fifth & sixth gate segments being between the seventh & eighth and ninth & tenth gate segments;

the third & fourth gate segments are correspondingly over the first and third ARs;

the seventh & eighth gate segments are correspondingly over the first and third ARs;

the fifth & sixth gate segments are correspondingly over the second and fourth ARs; and

the ninth & tenth gate segments are correspondingly over the second and fourth ARs.

10. The filler cell region of claim 5 , wherein:

each of the first and second gate segments is over the first AR-gap; and

each of the first and second gate segments is over the second AR-gap.

11. The filler cell region of claim 1 , further comprising:

active regions (ARs) extending in the second direction; and

wherein, relative to the second direction, first and second ones of the ARs extend continuously across the filler cell region.

12. A filler cell region in a semiconductor device, the filler cell region comprising:

gate segments extending in a first direction and being free from electrical coupling to active or passive circuitry within the filler cell region;

relative to the first direction:

a majority of first ends of the gate segments substantially aligning with a first reference line extending in a second direction perpendicular to the first direction, the first reference line being parallel and proximal to a top boundary of the filler cell region;

a majority of second ends of the gate segments substantially aligning with a second reference line extending in the second direction and being parallel and proximal to a bottom boundary of the filler cell region;

first and second ones of the gate segments extending continuously across the filler cell region; and

third & fourth and fifth & sixth ones of the gate segments being correspondingly coaxial and separated by corresponding gate-gaps located centrally in the filler cell region;

relative to the second direction, the first and second gate segments being between the third & fourth gate segments and the fifth & sixth gate segments;

relative to the first direction:

a first end of the first gate segment extending to the top boundary; and

a second end of the second gate segment extending to the bottom boundary;

at least additional four ones of the gate segments other than the first to sixth gate segments being arranged as pairs of dyads of gate segments, gate-segment-members of each dyad being coaxial and separated by a corresponding gate-gap relative to the first direction; and

relative to the second direction, the first and second gate segments, the third & fourth gate segments and the fifth & sixth gate segments being between each pair of dyads.

13. The filler cell region of claim 12 , wherein:

each dyad of gate segments includes an upper gate segment and a lower gate segment;

each pair of dyads includes a left dyad and a right dyad;

the third gate segment and each upper gate segment of each left dyad of gate segments is over the first AR;

the fourth gate segment and each lower gate segment of each left dyad of gate segments is over the third AR;

the fifth gate segment and each upper gate segment of each right dyad of gate segments is over the second AR; and

the sixth gate segment and each lower gate segment of each right dyad of gate segments is over the fourth AR.

14. A method of forming a filler cell region of a semiconductor device, the method comprising:

forming active regions (ARs) including doping areas of a substrate, the ARs extending in a first direction;

relative to the first direction, the forming ARs resulting in first & second and third & fourth ones of the ARs being correspondingly coaxial and separated by corresponding first and second AR-gaps located centrally in the filler cell region; and

forming gate segments extending in a second direction perpendicular to the first direction, the forming gate segments resulting in:

the gate segments being free from electrical coupling to active or passive circuitry within the filler cell region; and

relative to the second direction:

a majority of first ends of the gate segments substantially aligning with a first reference line extending in the first direction, the first reference line being parallel and proximal to a top boundary of the filler cell region;

a majority of second ends of the gate segments substantially aligning with a second reference line extending in the first direction and being parallel and proximal to a bottom boundary of the filler cell region;

first and second ones of the gate segments extending continuously across the filler cell region; and

third & fourth and fifth & sixth ones of the gate segments being correspondingly coaxial and separated by corresponding gate-gaps located centrally in the filler cell region;

relative to the first direction, the first and second gate segments being between the third & fourth gate segments and the fifth & sixth gate segments; and

relative to the second direction:

a first end of the first gate segment extending to the top boundary; and

a second end of the second gate segment extending to the bottom boundary.

15. The method of claim 14 , wherein the forming gate segments further results in:

the first and second gate segments being the same.

16. The method of claim 15 , wherein the forming gate segments further results in:

relative to the first direction, a seventh one of the gate segments being between the third & fourth gate segments and the fifth & sixth gate segments; and

relative to the second direction:

a first end of the seventh gate segment substantially aligning with the first reference line; and

a second end of the seventh gate segment substantially aligning with the second reference line.

17. The method of claim 14 , wherein the forming gate segments further results in:

relative to the second direction:

a second end of the first gate segment substantially aligning with the second reference line; and

a first end of the second gate segment substantially aligning with the first reference line.

18. The method of claim 14 , wherein:

the forming gate segments further results in:

relative to the first direction, a distance between two immediately adjacent ones of the gate segments being ≈1.0 CPP, where CPP is a unit of distance-measure; and

the forming ARs further results in:

a size of the first AR-gap, G1, between the first & second ARs is (≈1.5 CPP)≤G1; and

a size of the second AR-gap, G2, between the third & fourth ARs is (≈1.5 CPP)≤G2.

19. The method of claim 18 , wherein:

the forming gate segments further results in a configuration (A) or a configuration (B) being true;

for the configuration (A):

the first gate segment is over the first AR-gap and the second gate segment is over the second AR; and

the first gate segment is over the third AR and the second gate segment is over the second AR-gap; and

for the configuration (B):

the first gate segment is over the first AR and the second gate segment is over the first AR-gap; and

the first gate segment is over the second AR-gap and the second gate segment is over the fourth AR.

20. The method of claim 18 , wherein:

a configuration (A) or a configuration (B) being true;

for the configuration (A):

the first gate segment is over the first AR-gap; and

the second gate segment is over the second AR-gap; and

for the configuration (B):

the second gate segment is over the first AR-gap; and

the first gate segment is over the second AR-gap;

the forming gate segments results in:

relative to the second direction, seventh & eighth and ninth & tenth ones of the gate segments are correspondingly coaxial and separated by corresponding gate-gaps located centrally in the filler cell region;

relative to the first direction, the first and second gate segments, the third & fourth gate segments and the fifth & sixth gate segments being between the seventh & eighth and ninth & tenth gate segments;

the third & fourth and seventh & eighth gate segments are correspondingly over the first and third ARs; and

the fifth & sixth and ninth & tenth gate segments are correspondingly over the second and fourth ARs.