Integrated circuit including standard cell and method of fabricating the same
Provided is an integrated circuit including standard cells arranged over a plurality of rows. The standard cells may include: a plurality of functional cells each implemented as a logic circuit; and a plurality of filler cells including at least one first filler cell and at least one second filler cell that each include at least one pattern from among a back end of line (BEOL) pattern, a middle of line (MOL) pattern, and a front end of line (FEOL) pattern, and wherein the at least one first filler cell and the at least one second filler cell have a same size as each other, and a density of one of the at least one pattern of the at least one first filler cell is different from a density of one of the at least one pattern of the at least one second filler cell.
1 . An integrated circuit comprising standard cells arranged over a plurality of rows, wherein the standard cells comprise:
a plurality of functional cells each implemented as a logic circuit; and
a plurality of filler cells comprising at least one first filler cell and at least one second filler cell that each comprise at least one pattern from among a back end of line (BEOL) pattern, a middle of line (MOL) pattern, and a front end of line (FEOL) pattern, and
wherein the at least one first filler cell and the at least one second filler cell have a same size as each other, and a density of one of the at least one pattern of the at least one first filler cell is different from a density of one of the at least one pattern of the at least one second filler cell, and
wherein:
the at least one first filler cell and the at least one second filler cell comprise a same BEOL pattern, and a density of a contact included in the at least one first filler cell is different from a density of a contact included in the at least one second filler cell; or
the at least one first filler cell and the at least one second filler cell comprise a same FEOL pattern, and a density of a BEOL pattern included in the at least one first filler cell is different from a density of a BEOL pattern included in the at least one second filler cell; or
the at least one first filler cell and the at least one second filler cell comprise a same FEOL pattern, and the at least one second filler cell comprises at least a reference number of metal cuts set based on a density rule.
2 . The integrated circuit of claim 1 , wherein the at least one first filler cell and the at least one second filler cell comprise the same BEOL pattern, and the density of the contact included in the at least one first filler cell is different from the density of the contact included in the at least one second filler cell.
3 . The integrated circuit of claim 1 , wherein the at least one first filler cell and the at least one second filler cell comprise the same FEOL pattern, and the density of the BEOL pattern included in the at least one first filler cell is different from the density of the BEOL pattern included in the at least one second filler cell.
4 . The integrated circuit of claim 1 , wherein the at least one first filler cell and the at least one second filler cell comprise the same FEOL pattern, and the at least one second filler cell comprises at least the reference number of metal cuts set based on the density rule.
5 . The integrated circuit of claim 4 , wherein the at least one second filler cell is a plurality of second filler cells that are arranged from each other at a preset interval in a first direction or a second direction perpendicular to the first direction.
6 . An integrated circuit comprising standard cells arranged over a plurality of rows, wherein the standard cells comprise:
a plurality of functional cells each implemented as a logic circuit; and
a plurality of filler cells comprising at least one first filler cell and at least one second filler cell that each comprise at least one pattern from among a back end of line (BEOL) pattern, a middle of line (MOL) pattern, and a front end of line (FEOL) pattern, and
wherein the at least one first filler cell and the at least one second filler cell have a same size as each other, and a density of one of the at least one pattern of the at least one first filler cell is different from a density of one of the at least one pattern of the at least one second filler cell, and
wherein the at least one first filler cell is a plurality of first filler cells that are arranged over two or more consecutive rows, and comprise at least a reference number of metal cuts in a metal layer on which lines are provided, the lines extending in a direction perpendicular to an extending direction of the two or more consecutive rows.
7 . An integrated circuit comprising standard cells arranged over a plurality of rows, wherein the standard cells comprise:
a plurality of functional cells each implemented as a logic circuit; and
a plurality of filler cells comprising at least one first filler cell and at least one second filler cell that each comprise at least one pattern from among a back end of line (BEOL) pattern, a middle of line (MOL) pattern, and a front end of line (FEOL) pattern, and
wherein the at least one first filler cell and the at least one second filler cell have a same size as each other, and a density of one of the at least one pattern of the at least one first filler cell is different from a density of one of the at least one pattern of the at least one second filler cell,
wherein the at least one first filler cell comprises the MOL pattern,
wherein the MOL pattern of the at least one first filler cell comprises a first contact cut extending in a first direction, the first contact cut having a first length in the first direction,
wherein the at least one second filler cell comprises a second contact cut extending in the first direction, the second contact cut having a second length, and
wherein the first length is different from the second length.
8 . The integrated circuit of claim 7 , wherein
the at least one first filler cell further comprises a first active region comprising first source/drain contacts, and none of the first source/drain contacts are overlapped by the first contact cut, and
the at least one second filler cell further comprises a second active region comprising second source/drain contacts, and at least one of the second source/drain contacts is overlapped by the second contact cut.
9 . An integrated circuit comprising standard cells arranged over a plurality of rows, wherein the standard cells comprise:
a plurality of functional cells each implemented as a logic circuit; and
a plurality of filler cells comprising at least one first filler cell and at least one second filler cell that each comprise at least one pattern from among a back end of line (BEOL) pattern, a middle of line (MOL) pattern, and a front end of line (FEOL) pattern, and
wherein the at least one first filler cell and the at least one second filler cell have a same size as each other, and a density of one of the at least one pattern of the at least one first filler cell is different from a density of one of the at least one pattern of the at least one second filler cell,
wherein the at least one first filler cell comprises a first contact cut extending in a first direction, the first contact cut having a first length,
wherein the at least one second filler cell extends over a first section, a second section, and a third section in a second direction perpendicular to the first direction, and comprises a plurality of second contact cuts and a third contact cut,
wherein each of the plurality of second contact cuts extends in the first direction and has the first length, and second contact cuts of the plurality of second contact cuts are respectively provided in the first section and the third section,
wherein the third contact cut extends in the first direction and has a second length, and the third contact cut is provided in the second section, and
wherein the first length is less than the second length.
10 . An integrated circuit comprising standard cells arranged over a plurality of rows, wherein the standard cells comprise:
a plurality of functional cells each implemented as a logic circuit; and
a plurality of filler cells comprising at least one first filler cell and at least one second filler cell that each comprise at least one pattern from among a back end of line (BEOL) pattern, a middle of line (MOL) pattern, and a front end of line (FEOL) pattern, and
wherein the at least one first filler cell and the at least one second filler cell have a same size as each other, and a density of one of the at least one pattern of the at least one first filler cell is different from a density of one of the at least one pattern of the at least one second filler cell,
wherein the plurality of filler cells further comprise at least one third filler cell comprising patterns of a metal layer or a gate contact for adjusting a density of a pattern formed on at least one of the standard cells
wherein the at least one third filler cell is a plurality of third filler cells that are consecutively arranged, and
wherein at least one metal cut is formed in a bonding surface of the plurality of third filler cells that are consecutively arranged.