Integrated circuit (IC) design methods using engineering change order (ECO) cell architectures
Aspects disclosed in the detailed description include integrated circuit (IC) design methods using engineering change order (ECO) cell architectures. In particular, exemplary aspects provide a fill algorithm that is both single- and multi-row aware, considers a poly-pitch count, and utilizes metallization of the “empty space” relative to a suite of available fill cells. The algorithm is also aware of timing critical logic elements and may place ECO fill cells in near proximity to such timing sensitive circuits or other margin critical circuits to allow for decoupling or, if there is a logic error, an ECO cell is placed such that the ECO cell is well positioned to be repurposed as a delay circuit or other function to aid in margin control. For maximum flexibility, the algorithm may also address both pre- and post-route applications.
1. A non-transitory computer-readable medium having stored thereon computer executable instructions which, when executed by a processor, cause the processor to perform a method, the method comprising:
determining an initial circuit layout for an integrated circuit (IC);
determining empty space in the initial circuit layout;
placing a multi-row decoupling capacitor (DCAP) cell comprising a DCAP circuit in at least a first empty space in the initial circuit layout;
placing a single-row DCAP cell in at least a second empty space in the initial circuit layout;
generating a second circuit layout for the IC after the DCAP cells are placed; and
forming the multi-row DCAP cell from two vertically-stacked single-row engineering change order (ECO) logic cells.
2. The non-transitory computer-readable medium of claim 1 , wherein the method further comprises placing single-row engineering change order (ECO) logic cells in at least a third empty space in the initial circuit layout.
3. The non-transitory computer-readable medium of claim 1 , wherein the method further comprises placing fill pattern cells in at least a fourth empty space in the initial circuit layout.
4. The non-transitory computer-readable medium of claim 1 , wherein the method further comprises forming the single-row DCAP cell from an ECO logic cell.
5. The non-transitory computer-readable medium of claim 1 , wherein the method further comprises prioritizing placement of either DCAP cell based on a timing constraint.
6. The non-transitory computer-readable medium of claim 1 , wherein the method further comprises evaluating at least one metal layer of cells adjacent to a potential DCAP cell site in the IC before placing either DCAP cell.
7. The non-transitory computer-readable medium of claim 6 , wherein evaluating the at least one metal layer comprises evaluating an M1 or an M2 metal layer.
8. The non-transitory computer-readable medium of claim 6 , wherein evaluating the at least one metal layer comprises checking for blockages.
9. The non-transitory computer-readable medium of claim 1 , wherein the method further comprises checking the first empty space to see that the multi-row DCAP cell fits within the first empty space.
10. The non-transitory computer-readable medium of claim 9 , wherein checking the first empty space comprises checking to see if the first empty space is at least four (4) poly pitches wide along an x-axis direction.
11. The non-transitory computer-readable medium of claim 9 , wherein checking the first empty space comprises checking to see if the first empty space is at least as tall as an ECO cell height along a y-axis direction.
12. The non-transitory computer-readable medium of claim 9 , wherein the method further comprises placing a non-ECO single-row DCAP cell in the first empty space when an ECO cell does not fit within the first empty space.
13. The non-transitory computer-readable medium of claim 9 , wherein an ECO cell does not fit because of an adjacent metal layer.
14. The non-transitory computer-readable medium of claim 1 , wherein the method further comprises placing sufficient DCAP cells in the second circuit layout to allow a minimum DCAP usage.
15. The non-transitory computer-readable medium of claim 1 , wherein the method further comprises limiting placement of additional DCAP cells in the second circuit layout based on a maximum DCAP usage threshold.
16. The non-transitory computer-readable medium of claim 1 , wherein the method further comprises placing at least a third DCAP cell in a third empty space having a wiring density below a predefined threshold.
17. The non-transitory computer-readable medium of claim 1 , wherein the method further comprises evaluating regions of low wiring density at an M2 metal layer and placing ECO-based DCAPs in the regions of low wiring density.
18. The non-transitory computer-readable medium of claim 1 , wherein the method further comprises using a cell library that defines the multi-row DCAP cell and the single row DCAP cell.
19. The non-transitory computer-readable medium of claim 1 , wherein the method further comprises forming the single-row DCAP cell from two horizontally-adjacent ECO logic cells.