Methods of forming semiconductor devices
In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.
1. A method comprising:
forming a dielectric material over a source/drain region;
forming a first gate mask adjacent to the dielectric material and the source/drain region;
depositing a first filling layer over the first gate mask and the dielectric material;
depositing a second filling layer over the first filling layer;
planarizing the second filling layer with a chemical mechanical polish process, the chemical mechanical polish process being performed until the first filling layer is exposed; and
planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer and the second filling layer at the same rate, wherein a top surface of the first filling layer is level with a top surface of the dielectric material after the etch-back process.
2. The method of claim 1 , wherein a top surface of the first gate mask extends above the top surface of the dielectric material before the etch-back process.
3. The method of claim 2 , wherein a top surface of the first gate mask is level with the top surface of the dielectric material after the etch-back process.
4. The method of claim 1 , wherein the top surface of the dielectric material extends above a top surface of the first gate mask before the etch-back process.
5. The method of claim 4 , wherein the first filling layer is over the first gate mask after the etch-back process.
6. The method of claim 1 , wherein the first gate mask is formed on a gate electrode, the method further comprising:
replacing a portion of the first filling layer with a second gate mask on the gate electrode.
7. The method of claim 1 , wherein the first filling layer acts as a chemical mechanical polish stop layer for the chemical mechanical polish process.
8. A method comprising:
forming a dielectric material over a first source/drain region and a second source/drain region;
forming a first gate mask and a second gate mask adjacent to the first source/drain region and the second source/drain region, respectively, the first gate mask having a first width, the second gate mask having a second width, the second width being different from the first width;
depositing a filling material over the first gate mask, the second gate mask, and the dielectric material;
planarizing the filling material with a chemical mechanical polish process; and
after the chemical mechanical polish process, planarizing the filling material with an etch-back process, the etch-back process etching the filling material and the dielectric material at the same rate, wherein top surfaces of the filling material and the dielectric material are level after the etch-back process.
9. The method of claim 8 further comprising:
replacing the filling material with a third gate mask and a fourth gate mask adjacent to the first source/drain region and the second source/drain region, respectively.
10. The method of claim 8 , wherein the filling material is silicon.
11. The method of claim 8 , wherein top surfaces of the first gate mask and the second gate mask are level with the top surfaces of the dielectric material and the filling material after the etch-back process.
12. The method of claim 8 , wherein the filling material is over top surfaces of the first gate mask and the second gate mask after the etch-back process.
13. A method comprising:
patterning a dielectric material with a first opening;
forming a first gate structure in the first opening;
depositing a first filling layer over the first gate structure and the dielectric material;
planarizing the first filling layer with a chemical mechanical polish process, wherein the first filling layer is over the dielectric material after the chemical mechanical polish process;
planarizing the first filling layer with an etch-back process, wherein top surfaces of the dielectric material and the first filling layer are level after the etch-back process;
replacing a portion of the first filling layer over the first gate structure with a gate mask; and
forming a gate contact through the gate mask to contact the first gate structure.
14. The method of claim 13 further comprising:
patterning the first filling layer and the first gate structure with a second opening;
depositing a second filling layer in the second opening and over the first filling layer; and
planarizing the second filling layer with the chemical mechanical polish process.
15. The method of claim 14 , wherein the first filling layer comprises silicon and the second filling layer comprises silicon nitride.
16. The method of claim 13 , wherein the etch-back process is a dry etch performed in an oxygen-free environment.
17. The method of claim 16 , wherein the dry etch is performed with NF 3 and H 2 .
18. The method of claim 13 further comprising:
patterning the dielectric material with a second opening;
forming a second gate structure in the second opening, the first gate structure having a first width, the second gate structure having a second width, the second width being greater than the first width; and
depositing the first filling layer over the second gate structure.
19. The method of claim 18 , wherein the first gate structure is disposed on a semiconductor fin and the second gate structure is disposed on the semiconductor fin.
20. The method of claim 13 further comprising:
depositing the dielectric material on an interlayer dielectric.