Gate structures in transistor devices and methods of forming same
A method includes forming a first source/drain region and a second source/drain region in a semiconductor fin; depositing a first dielectric layer over the first source/drain region and the second source/drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.
1. A method comprising:
forming a first source/drain region and a second source/drain region in a semiconductor fin;
depositing a first dielectric layer over the first source/drain region and the second source/drain region;
etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer;
forming first sidewall spacers on sidewalls of the opening; and
forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.
2. The method of claim 1 , wherein a width of the opening in a lower region of the opening decreases in width in a direction towards the semiconductor fin.
3. The method of claim 1 , wherein an interface between the first sidewall spacers and the first dielectric layer is curved.
4. The method of claim 1 , wherein an interface between the first sidewall spacers and the gate stack is curved.
5. The method of claim 1 further comprising:
prior to depositing the first dielectric layer depositing a contact etch stop layer (CESL) on an upper surface of the semiconductor fin, over the first source/drain region, and over the second source/drain region, wherein etching the opening comprises etching the CESL.
6. The method of claim 5 , wherein:
depositing the first dielectric layer comprises depositing a portion of the first dielectric layer to extend continuously from the first source/drain region to the second source/drain region;
depositing the CESL comprises depositing a portion of the CESL to extend continuously from the first source/drain region to the second source/drain region; and
etching the opening comprises removing the portion of the first dielectric layer and removing the portion of the CESL.
7. The method of claim 1 , wherein a thickness of each of the first sidewall spacers is in a range of 2 nm to 10 nm.
8. The method of claim 1 further comprising recessing the gate stack and forming an insulating gate mask over the gate stack.
9. A device comprising:
a semiconductor fin extending from a semiconductor substrate;
a first source/drain region and a second source/drain region in the semiconductor fin;
an interlayer dielectric over the semiconductor substrate;
a gate stack between the first source/drain region and the second source/drain region, wherein at least a lower portion of the gate stack decreases in width in a direction towards the semiconductor substrate;
a first source/drain contact extending through the interlayer dielectric to the first source/drain region;
a second source/drain contact extending through the interlayer dielectric to the second source/drain region;
a first sidewall spacer between the gate stack and the first source/drain contact; and
a second sidewall spacer between the gate stack and the second source/drain contact, wherein the first sidewall spacer and the second sidewall spacer each decrease in width in a direction towards the semiconductor substrate.
10. A method comprising:
forming a first source/drain region and a second source/drain region in a semiconductor fin;
depositing a contact etch stop layer over the semiconductor fin, the first source/drain region, and the second source/drain region;
depositing a first dielectric layer over the contact etch stop layer;
etching the first dielectric layer and the contact etch stop layer to form an opening that exposes the semiconductor fin, wherein after forming the opening, the first dielectric layer comprises a footing region with a curved sidewall that extends into the opening; and
forming a gate stack in the opening, wherein at least a lower portion of the gate stack tapers in width in a direction towards the semiconductor fin.
11. The method of claim 10 , wherein a lateral distance between a vertical sidewall of the first dielectric layer and a farthest point that the footing region extends into the opening is in a range of 0.5 nm to 2 nm.
12. The method of claim 10 further comprising:
depositing a spacer layer on sidewalls and a bottom surface of the opening; and
etching the spacer layer to form sidewall spacers on sidewalls of the opening.
13. The method of claim 12 , wherein a thickness of the spacer layer is in a range of 2 nm to 10 nm.
14. The method of claim 12 , wherein at least a lower portion of each of the sidewall spacers tapers in width in a direction towards the semiconductor fin.
15. The method of claim 10 further comprising:
forming a first source/drain contact through the first dielectric layer, wherein the first source/drain contact is electrically connected to the first source/drain region; and
forming a second source/drain contact through the first dielectric layer, wherein the second source/drain contact is electrically connected to the second source/drain region.
16. The device of claim 9 , wherein a thickness of the first sidewall spacer is in a range of 2 nm to 10 nm, and wherein a thickness of the second sidewall spacer is in a range of 2 nm to 10 nm.
17. The device of claim 9 further comprising a contact etch stop layer on a top surface of the semiconductor fin, wherein the contact etch stop layer is disposed directly under the gate stack.
18. The device of claim 9 , wherein the lower portion of the gate stack has a curved sidewall.
19. The device of claim 9 , wherein the first source/drain contact extends directly under a lower portion of the first sidewall spacer.
20. The device of claim 9 , wherein the first source/drain contact extends directly under the lower portion of the gate stack.