Device-to-device connection with multiple parallel ground pins
Examples described herein relate to a pin arrangement that includes a first signal pin; a second signal pin; and multiple parallel ground pins positioned between the first and second signal pins. In some examples, the multiple parallel ground pins are coupled to a single pin connector coupled to a first device and a single pin connector coupled to a second device. In some examples, a first leg of the multiple parallel ground pins is positioned parallel to a portion of the first signal pin and wherein a second leg of the multiple parallel ground pins is positioned parallel to a portion of the second signal pin. In some examples, the multiple parallel ground pins provide a 1:N signal to ground ratio for signals transmitted through at least a portion of the first and second signal pins, where N is greater than 1.
1. An apparatus comprising:
a first signal pin;
a second signal pin; and
multiple parallel ground pins positioned between the first and second signal pins, the multiple parallel ground pins coupled to a first single pin contact region coupled to a first device and a second single pin contact region coupled to a second device, wherein
the first device comprises a motherboard,
the first single pin contact region is coupled to a surface mount technology (SMT) connector of the motherboard,
the second device comprises a dual in-line memory module (DIMM),
the first device is oriented perpendicular to the second device,
the second single pin contact region is coupled to a gold finger connector in the DIMM,
a first leg of the multiple parallel ground pins is positioned parallel to a portion of the first signal pin,
a second leg of the multiple parallel ground pins is positioned parallel to a portion of the second signal pin,
the first leg and the second leg join to form the first single pin contact region at a first end,
the first leg and the second leg join to form the second single pin contact region at a second end,
the first and second signal pins are positioned parallel and are coupled to respective SMT connectors in the first device and respective gold finger connectors in the second device, and
the multiple parallel ground pins provide a 1:N signal to ground ratio for signals transmitted through at least a portion of the first and second signal pins, where N is greater than 1.
2. The apparatus of claim 1 , wherein the multiple parallel ground pins comprise two or more ground pins oriented parallel to each other.
3. The apparatus of claim 1 , wherein the multiple parallel ground pins comprise one or more of: copper, bronze, or an alloy.
4. The apparatus of claim 1 , wherein an arrangement of contact regions is consistent with Double Data Rate version 5 (DDR5).
5. The apparatus of claim 1 , further comprising the first device and the second device, and one or more of: central processing unit (CPU), XPU, graphics processing unit (GPU) coupled to the motherboard and to receive data using the first single pin contact region and the second single pin contact region.
6. A method comprising:
transmitting a first signal through a first signal pin from a first device to a second device;
transmitting a second signal through a second signal pin from the first device to the second device; and
providing reduction of near end cross talk and far end cross talk between the first and second signals using a ground pin with multiple parallel ground pins connected to a single pin contact region with the first device and connected to a second single pin contact region with the second device, wherein:
the first single pin contact region is coupled to a surface mount technology (SMT) connector of the first device,
the first device is oriented perpendicular to the second device,
the second single pin contact region is coupled to a gold finger connector in the second device,
a first leg of the multiple parallel ground pins is positioned parallel to a portion of the first signal pin,
a second leg of the multiple parallel ground pins is positioned parallel to a portion of the second signal pin,
the first leg and the second leg join to form the first single pin contact region at a first end,
the first leg and the second leg join to form the second single pin contact region at a second end, and
the first and second signal pins are positioned parallel and are coupled to respective SMT connectors in the first device and respective gold finger connectors in the second device.
7. The method of claim 6 , wherein an arrangement of the SMT connectors and gold finger connectors is consistent with Double Data Rate version 5 (DDR5).
8. The method of claim 6 , wherein the multiple parallel ground pins provide a 1:N signal to ground ratio for signals transmitted through at least a portion of the first and second signal pins, where N is greater than 1.
9. The method of claim 6 , wherein the multiple parallel ground pins comprise two or more ground pins oriented parallel to each other.
10. The method of claim 6 , wherein the multiple parallel ground pins comprise one or more of: copper, bronze, or an alloy.
11. The method of claim 6 , wherein
the first device comprises a motherboard and
the second device comprises a dual in-line memory module (DIMM) and comprising one or more of: central processing unit (CPU), XPU, graphics processing unit (GPU) coupled to the motherboard and to receive data using the first signal pin and the second signal pin.
12. A system comprising:
a first device comprising a motherboard;
a second device comprising a dual in-line memory module (DIMM);
a first signal pin;
a second signal pin; and
multiple parallel ground pins positioned between the first and second signal pins, the multiple parallel ground pins coupled to a first single pin contact region coupled to the first device and a second single pin contact region coupled to the second device, wherein:
the first device comprises a motherboard,
the first single pin contact region is coupled to a surface mount technology (SMT) connector of the motherboard,
the second device comprises a dual in-line memory module (DIMM),
the first device is oriented perpendicular to the second device,
the second single pin contact region is coupled to a gold finger connector in the DIMM,
a first leg of the multiple parallel ground pins is positioned parallel to a portion of the first signal pin,
a second leg of the multiple parallel ground pins is positioned parallel to a portion of the second signal pin,
the first leg and the second leg join to form the first single pin contact region at a first end,
the first leg and the second leg join to form the second single pin contact region at a second end, and
the first and second signal pins are positioned parallel and are coupled to respective SMT connectors in the first device and respective gold finger connectors in the second device.
13. The system of claim 12 , wherein an arrangement of contact regions pin connectors is consistent with Double Data Rate version 5 (DDR5).
14. The system of claim 12 , wherein the multiple parallel ground pins comprise two or more ground pins oriented parallel to each other.
15. The system of claim 12 , wherein the multiple parallel ground pins provide a 1:N signal to ground ratio for signals transmitted through at least a portion of the first and second signal pins, where N is greater than 1.