Systems for error reduction of encoded data using neural networks
Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks to estimate an error-reduced version of encoded data based on a retrieved version of encoded data (e.g., data encoded using one or more encoding techniques) from a memory. The neural networks and/or recurrent neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing a neural network or recurrent neural network to estimate an error-reduced version of encoded data for an error correction coding (ECC) decoder, e.g., to facilitate decoding of the error-reduced version of encoded data at the decoder. In this manner, neural networks or recurrent neural networks described herein may be used to improve or facilitate aspects of decoding at ECC decoders, e.g., by reducing errors present in encoded data due to storage or transmission.
1. An apparatus comprising:
a memory configured to store encoded data; and
a neural network configured to receive, from the memory, the encoded data including at least one error bit and further configured to mix the encoded data received from the memory with at least a portion of a plurality of coefficients selected for error reduction of data retrieved from the memory to generate an estimate of an error-reduced version of the encoded data, wherein the neural network comprises at least one stage configured to provide delayed versions of respective outputs and mix the delayed versions of the respective outputs with at least a portion of the encoded data.
2. The apparatus of claim 1 , further comprising an encoder configured to provide the encoded data to the memory in accordance with an encoding technique.
3. The apparatus of claim 1 , wherein the error-reduced version of the encoded data corresponds to the encoded data received from the memory without the at least one error bit.
4. The apparatus of claim 1 , wherein the neural network comprises at least two stages to generate the error-reduced version of the encoded data.
5. The apparatus of claim 1 , wherein the error-reduced version of the encoded data includes a reduction of a bit error rate (BER) or an increase of a signal-to-noise ratio (SNR) as compared to a respective BER or SNR of the stored version of the encoded data.
6. The apparatus of claim 1 , further comprising a decoder configured to receive the error-reduced version of the encoded data and to provide decode data based on the error-reduced version of the encoded data.
7. An apparatus comprising:
a memory configured to store encoded data; and
a neural network configured to receive, from the memory, the encoded data including at least one error bit, and further configured to mix the encoded data received from the memory with at least a portion of a plurality of coefficients selected for error reduction of data retrieved from the memory to generate an estimate of an error-reduced version of the encoded data, wherein the neural network comprises at least two stages to generate the error-reduced version of the encoded data, the at least two stages comprising:
a first stage of circuitry configured to receive the encoded data from the memory, to combine the received encoded data with a first set of predetermined weights, and to evaluate at least one non-linear function using combinations of the received encoded data and delayed versions of the combinations of the received encoded data to provide intermediate data; and
a second stage of circuitry configured to receive the intermediate data and combine the intermediate data using a second set of predetermined weights to generate the error-reduced version of the encoded data.
8. The apparatus of claim 7 , wherein the first and second sets of predetermined weights were trained for error reduction of data retrieved from the memory.
9. The apparatus of claim 7 , wherein the first and second sets of predetermined weights are based on training of a neural network using known errored-encoded data and encoded data pairs, the known errored-encoded data including at least one error bit.
10. The apparatus of claim 8 , wherein the first stage of circuitry further comprises a first plurality of memory look-up units (MLUs), the first plurality of MLUs each configured to retrieve at least one intermediate data value corresponding to an output of a respective one of the first plurality of multiplication/accumulation units based on the at least one non-linear function.
11. The apparatus of claim 10 , wherein the decoder is configured to decode encoded data in accordance with an error-correction code decoding technique.
12. The apparatus of claim 10 , wherein the decoder comprises an iterative decoder configured to decode encoded data in accordance with an error-correction code iterative decoding technique.
13. An apparatus comprising:
a memory configured to store encoded data; and
a neural network configured to receive, from the memory, the encoded data including at least one error bit, and further configured to mix the encoded data received from the memory with at least a portion of a plurality of coefficients selected for error reduction of data retrieved from the memory to generate an estimate of an error-reduced version of the encoded data, wherein the neural network comprises at least two stages to generate the error-reduced version of the encoded data, wherein the at least two stages include a first stage of circuitry comprising a first plurality of multiplication/accumulation units, the first plurality of multiplication/accumulation units each configured to multiply at least one bit of the received encoded data with at least one of the first set of predetermined weights and sum multiple weighted bits of the encoded data.
14. A method comprising:
mixing, at a first stage of a neural network, a first version of encoded data retrieved from a memory and delayed versions of respective outputs of the first stage of the neural network with a first subset of a plurality of coefficients selected for error reduction of data retrieved from the memory to generate first processing results;
mixing, at second stage of the neural network, the first processing results and delayed versions of at least a portion of the first processing results with a second subset of the plurality of coefficients to generate second processing results; and
generating, by the neural network, an estimate of an error-reduced version of the encoded data based on the second processing results.
15. The method of claim 14 , further comprising delaying, at respective delay units associated with the first stage of the neural network, the outputs of the first stage of the neural network to generate the delayed versions of the respective outputs of the first stage of the neural network.
16. The method of claim 14 , further comprising multiplying the first version of the encoded data and the delayed versions of the respective outputs of the first stage of the neural network with the first subset of the plurality of coefficients to generate the first processing results.
17. The method of claim 14 , further comprising obtaining the first version of the encoded data from the memory.
18. The method of claim 17 , wherein the stored version of the encoded data includes at least one error bit.
19. The method of claim 14 , further comprising:
decoding the error-reduced version of the encoded data to provide decoded data; and
writing the decoded data to or reading the decoded data from the memory.
20. The method of claim 14 , wherein the error-reduced version of the encoded data is an estimate of the encoded data relative to output of an encoder associated with an encoding technique.