Granted Patent B2

US 12,242,387 · App. 17/726,100 · Granted Mar 4, 2025

Inventor: Yang Seok Ki (Palo Alto, CA)

Assignee: Samsung Electronics Co., Ltd.

G06F12/1054G06F2212/7201

Abstract

Claims (58)

1. A method for managing memory, the method comprising:

generating a first data structure associated with one or more virtual addresses mapped to one or more physical addresses of the memory, wherein the first data structure is configured to implement a circular buffer, and wherein a size of the first data structure is based on a characteristic of the memory;

receiving, from a storage device coupled to a processor, data to be stored in the memory;

identifying a virtual address of the one or more virtual addresses based on the first data structure;

mapping the virtual address to a physical address;

storing the data in the physical address; and

updating identification of a first location of the first data structure based on the storing of the data, wherein the storage device provides the identification of the first location;

retrieving the data from the memory based on a request by the processor; and

updating identification of a second location of the first data structure based on the retrieving of the data, wherein the processor provides the identification of the second location.

2. The method of claim 1 , wherein the memory includes a set associative cache memory.

3. The method of claim 1 , wherein the first data structure is configured to track production and consumption of data in and out of the memory based on an eventual consistency model.

4. The method of claim 1 , wherein the size of the first data structure is based on at least one of a size of the memory, a placement policy used by the memory, or a number of processors having access to the memory.

5. The method of claim 1 , wherein the size is a cache line size.

6. The method of claim 1 further comprising:

generating, by a storage device, a second data structure, wherein the second data structure is based on the first data structure;

updating, by the storage device, the second data structure in response to producing the data; and

transmitting a message to a host computing device in response to the updating of the second data structure, for updating the first data structure, wherein the first data structure and the second data structure adhere to an eventual consistency model.

7. The method of claim 1 further comprising:

identifying a virtual address of the first data structure storing the data;

mapping the virtual address to the physical address of the memory;

retrieving the data from the physical address of the memory; and

updating the first data structure based on the retrieving of the data.

8. The method of claim 7 further comprising:

generating, by a storage device, a second data structure, wherein the second data structure is based on the first data structure;

receiving, by the storage device, a message from a host computing device in response to the updating of the first data structure; and

updating, by the storage device, the second data structure in response to the message from the host computing device, wherein the first data structure and the second data structure adhere to an eventual consistency model.

9. A host computing device comprising:

a memory; and

a processor coupled to the memory, wherein the processor includes logic for:

generating a first data structure associated with one or more virtual addresses mapped to one or more physical addresses of the memory, wherein the first data structure is configured to implement a circular buffer, and wherein a size of the first data structure is based on a characteristic of the memory;

receiving, from a storage device coupled to the processor, data to be stored in the memory;

identifying a first virtual address of the one or more virtual addresses based on the first data structure;

mapping the first virtual address to a first physical address;

storing the data in the first physical address, wherein identification of a first location of the first data structure is updated based on the storage device providing the data to be stored, wherein the storage device provides the identification of the first location;

retrieving the data from the memory;

based on the retrieving of the data:

identifying a second location of the first data structure; and

updating identification of the second location of the first data structure.

10. The host computing device of claim 9 , wherein the memory includes a set associative cache memory.

11. The host computing device of claim 9 , wherein the first data structure is configured to track production and consumption of data in and out of the memory based on an eventual consistency model.

12. The host computing device of claim 9 , wherein the size of the first data structure is based on at least one of a size of the memory, a placement policy used by the memory, or a number of processors having access to the memory.

13. The host computing device of claim 9 , wherein the size is a cache line size.

14. The host computing device of claim 9 , wherein the processor includes logic for:

identifying the first virtual address of the first data structure storing the data;

mapping the first virtual address to the first physical address of the memory;

retrieving the data from the first physical address of the memory; and

updating the first data structure based on the retrieving of the data.

15. A storage device coupled to a host computing device having a memory, the storage device comprising:

a non-transitory storage medium; and

a processor coupled to the non-transitory storage medium, the processor having logic for:

producing data;

identifying a virtual address of one or more virtual addresses of a data structure, wherein the virtual address is mapped to a physical address of the memory of the host computing device, wherein the data structure is configured to implement a circular buffer, and wherein a size of the data structure is based on a characteristic of the memory;

storing the data in the physical address;

based on the storing of the data:

identifying a first location of the data structure;

updating identification of the first location of the data structure; and

providing the identification of the first location to the host computing device,

wherein, the host computing device is configured to retrieve the data from the memory, update identification of a second location of the data structure based on the host computing device retrieving the data, and provide the identification of the second location to the processor.

Assignments (1)

Continuity (2)

References Cited (39)