Gate driving circuit and display device
The present disclosure provides a gate driving circuit and a display device. An nth stage circuit among a plurality of stage circuits included in a gate driving circuit according to embodiments of the disclosure may include a scan output buffer circuit configured to output a scan signal according to voltages of a Q node and a Qb node, a control circuit including a plurality of transistors to control the voltages of the Q node and the Qb node, the plurality of transistors including a first Q node discharge transistor turned on or off by the voltage of the Qb node to control connection between the Q node and a low-potential voltage node, and a body bias circuit configured to supply a body bias voltage to a body of a first Q node discharge transistor.
1. A gate driving circuit, comprising:
a plurality of stage circuits configured to output a plurality of scan signals, an nth stage circuit among the plurality of stage circuits including:
a scan output buffer circuit configured to receive a scan clock signal from a scan clock node, receive a low-potential voltage from a low-potential voltage node, and output a scan signal including a first signal section having a turn-off level voltage and a second signal section having a turn-on level voltage according to voltages of a Q node and a Qb node;
a control circuit including a plurality of transistors to control the voltages of the Q node and the Qb node to control an operation of the scan output buffer circuit, the plurality of transistors including a first Q node discharge transistor turned on or off by the voltage of the Qb node to control connection between the Q node and the low-potential voltage node; and
a body bias circuit configured to supply a body bias voltage to a body of the first Q node discharge transistor.
2. The gate driving circuit of claim 1 , wherein a voltage level of the body bias voltage changes according to a state of the first Q node discharge transistor.
3. The gate driving circuit of claim 2 , wherein during a period when the first Q node discharge transistor is to be turned off, the body bias voltage has a first voltage level, and during a period when the first Q node discharge transistor is to be turned on, the body bias voltage has a second voltage level different from the first voltage level.
4. The gate driving circuit of claim 3 , wherein the first voltage level is lower than the second voltage level, and the first voltage level is lower than the low-potential voltage.
5. The gate driving circuit of claim 1 , wherein a voltage level change pattern of the body bias voltage corresponds to a voltage level change pattern of the Qb node.
6. The gate driving circuit of claim 5 , wherein when the Qb node has a low level voltage, the body bias voltage has a first voltage level, and when the Qb node has a high level voltage, the body bias voltage has a second voltage level higher than the first voltage level.
7. The gate driving circuit of claim 1 , wherein the body bias voltage has a voltage level that varies depending on an operating state of the scan output buffer circuit.
8. The gate driving circuit of claim 7 , wherein when the scan signal output from the scan output buffer circuit is the second signal section having the turn-on level voltage, the body bias voltage has a first voltage level, and when the scan signal output from the scan output buffer circuit is the first signal section having the turn-off level voltage, the body bias voltage has a second voltage level different from the first voltage level.
9. The gate driving circuit of claim 1 , wherein the body bias circuit includes:
a first bias capacitor connected between a body of the first Q node discharge transistor and a global low-potential voltage node to which a global low-potential voltage is applied; and
a second bias capacitor connected between the body of the first Q node discharge transistor and the Qb node.
10. The gate driving circuit of claim 9 , wherein the second bias capacitor has a larger capacitance than the first bias capacitor.
11. The gate driving circuit of claim 9 , wherein the global low-potential voltage is lower than the low-potential voltage.
12. The gate driving circuit of claim 1 , wherein the scan output buffer circuit includes:
a scan pull-up transistor turned on or off according to the voltage of the Q node to control connection between a scan clock node to which a scan clock signal is input and a scan output node to which the scan signal is output; and
a scan pull-down transistor turned on or off according to the voltage of the Qb node to control connection between the scan output node and the low-potential voltage node, wherein the control circuit includes:
a Q node charging circuit configured to charge the Q node;
a Q node discharging circuit configured to discharge the Q node; and
an inverter circuit configured to charge and discharge the Qb node, and
wherein the first Q node discharge transistor is included in the Q node discharge circuit.
13. The gate driving circuit of claim 12 , wherein the Q node charging circuit includes a Q node charge transistor turned on or turned off by a previous carry signal output from a previous stage circuit to control connection between a previous carry node to which the previous carry signal is input and the Q node, wherein the Q node discharging circuit includes:
the first Q node discharge transistor turned on or off according to the voltage of the Q node to control connection between the Q node and the low-potential voltage node; and
a second Q node discharge transistor turned on or off by a next carry signal output from a next stage circuit to control connection between the Q node and the low-potential voltage node, and
wherein the body of the first Q node discharge transistor and a body of the second Q node discharge transistor are electrically connected to each other.
14. The gate driving circuit of claim 12 , wherein the inverter circuit includes:
a first Qb node charge transistor controlling connection between a high-potential voltage node to which a high-potential voltage is applied and the Qb node; and
a first Qb node discharge transistor controlling connection between the Qb node and the low-potential voltage node.
15. The gate driving circuit of claim 14 , wherein the inverter circuit further includes a second Qb node discharge transistor controlling connection between the Qb node and the low-potential voltage node, and
wherein the first Qb node discharge transistor is turned on or off by the previous carry signal, and the second Qb node discharge transistor is turned on or off according to the voltage of the Q node.
16. The gate driving circuit of claim 15 , wherein the inverter circuit further includes:
a first control transistor controlled according to the high-potential voltage to control connection between a gate node of the first Qb node charge transistor and the high-potential voltage node; and
a second control transistor turned on or off according to the voltage of the Q node to control connection between the gate node of the first Qb node charge transistor and the low-potential voltage node.
17. The gate driving circuit of claim 12 , wherein the control circuit further includes a sensing control circuit controlling the voltage of the Q node so that the scan output buffer circuit outputs the scan signal including the second signal section having the turn-on level voltage during an arbitrary blank period.
18. A display device, comprising:
a substrate;
a plurality of subpixels disposed on the substrate;
a plurality of scan signal lines connected to the plurality of subpixels; and
a gate driving circuit connected to the plurality of scan signal lines, wherein the gate driving circuit includes a plurality of stage circuits, and wherein an nth stage circuit among the plurality of stage circuits includes:
a scan output buffer circuit configured to receive a scan clock signal from a scan clock node, receive a low-potential voltage from a low-potential voltage node, and output a scan signal including a first signal section having a turn-off level voltage and a second signal section having a turn-on level voltage according to voltages of a Q node and a Qb node;
a control circuit including a plurality of transistors to control the voltages of the Q node and the Qb node to control an operation of the scan output buffer circuit, the plurality of transistors including a first Q node discharge transistor turned on or off by the voltage of the Qb node to control connection between the Q node and the low-potential voltage node; and
a body bias circuit configured to supply a body bias voltage to a body of the first Q node discharge transistor.
19. The display device of claim 18 , wherein a voltage level of the body bias voltage changes according to a state of the first Q node discharge transistor.
20. The display device of claim 18 , wherein the body bias voltage has a voltage level that changes according to the voltage level of the Ob node.