FinFET device having a gate with a tapering bottom portion and a gate fill material with a widening bottom portion
A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.
1. A semiconductor device comprising:
a fin protruding above a substrate;
isolation regions on opposing sides of the fin;
a gate structure over the fin;
gate spacers along sidewalls of the gate structure; and
a gate fill material between the gate structure and the gate spacers, wherein a distance, measured between opposing sidewalls of the gate fill material facing the gate structure, decreases as the gate fill material extends toward the isolation regions, wherein the gate fill material comprises:
a first portion over an upper surface of the fin distal from the substrate, wherein a first thickness of the first portion remains a same as the first portion extends from an upper surface of the gate spacers to the upper surface of the fin; and
a second portion below the upper surface of the fin, wherein a second thickness of the second portion increases as the second portion extends toward the isolation regions.
2. The semiconductor device of claim 1 , wherein the gate structure comprises:
a gate electrode;
a work function layer around the gate electrode;
a barrier layer around the work function layer; and
a gate dielectric layer around the barrier layer, wherein the gate dielectric layer contacts the gate fill material.
3. The semiconductor device of claim 2 , wherein the gate fill material is a first dielectric material different from a second dielectric material of the gate spacers.
4. The semiconductor device of claim 1 , wherein the gate fill material is disposed on the isolation regions and contacts the isolation regions.
5. The semiconductor device of claim 4 , wherein the gate fill material extends continuously along sidewalls of the gate spacers from the upper surface of the gate spacers distal from the isolation regions to the isolation regions.
6. The semiconductor device of claim 1 , wherein a bottom portion of the gate structure contacts the isolation regions and the gate fill material, wherein a width of the bottom portion of the gate structure decreases as the gate structure extends toward the isolation regions.
7. The semiconductor device of claim 6 , wherein a bottom surface of the gate structure faces and contacts the isolation regions, wherein the bottom surface of the gate structure is a curved surface and extends into the isolation regions.
8. The semiconductor device of claim 7 , wherein a center of the bottom surface of the gate structure extends deeper into the isolation regions than an edge of the bottom surface of the gate structure.
9. A semiconductor device comprising:
isolation regions over a substrate;
a fin protruding above the isolation regions;
a gate structure over the fin, wherein an upper portion of the gate structure has a uniform thickness, and a lower portion of the gate structure tapers off as the lower portion of the gate structure extends toward the isolation regions;
gate spacers along sidewalls of the gate structure; and
a gate fill material between and contacting the gate structure and the gate spacers, wherein a thickness of the gate fill material increases as the gate fill material extends toward the isolation regions.
10. The semiconductor device of claim 9 , wherein a lower surface of the gate structure contacts the isolation regions, wherein the lower surface of the gate structure is a curved surface.
11. The semiconductor device of claim 10 , wherein a lower surface of the gate fill material contacts the isolation regions, wherein the lower surface of the gate fill material is a flat surface.
12. The semiconductor device of claim 10 , wherein the lower surface of the gate structure extends into the isolation regions.
13. The semiconductor device of claim 9 , wherein the gate fill material contacts and extends continuously along sidewalls of the gate spacers from upper surfaces of the gate spacers distal from the substrate to the isolation regions.
14. The semiconductor device of claim 9 , wherein the gate fill material has an upper portion distal from the isolation regions and has a lower portion contacting the isolation regions, wherein the upper portion of the gate fill material has a uniform thickness, and the lower portion of the gate fill material has a thickness that increases continuously as the lower portion of the gate fill material extends toward the isolation regions.
15. The semiconductor device of claim 9 , wherein an upper surface of the isolation regions has a first region and a second region, wherein the first region contacts a lower surface of the gate fill material facing the isolation regions, and the second region contacts a lower surface of the gate structure facing the isolation regions, wherein the first region is a flat surface, and the second region is a curved surface.
16. The semiconductor device of claim 15 , wherein the second region extends closer to the substrate than the first region.
17. A semiconductor device comprising:
isolation regions over a substrate;
a fin between the isolation regions and protruding above the isolation regions;
a gate structure over the fin, wherein a lower portion of the gate structure extends into the isolation regions;
gate spacers on opposing sides of the gate structure; and
a gate fill material between the gate structure and the gate spacers, wherein the gate fill material comprises an upper portion distal from the isolation regions and a lower portion contacting the isolation regions, wherein the upper portion of the gate fill material has a uniform thickness, and the lower portion of the gate fill material has a thickness that increases as the gate fill material extends toward the isolation regions.
18. The semiconductor device of claim 17 , wherein a thickness of the lower portion of the gate structure, measured between opposing sidewalls of the lower portion of the gate structure, decreases as the lower portion of the gate structure extends toward the isolation regions.
19. The semiconductor device of claim 17 , wherein the gate fill material contacts the lower portion of the gate structure and the gate spacers.
20. The semiconductor device of claim 19 , wherein the gate fill material extends along sidewalls of the gate spacers from an upper surface of the gate spacers distal from the substrate to the isolation regions.