Devices, systems, and methods for stacked die packages
A package includes a first chip stack. The first chip stack includes a first chip including first bonding structures, a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures, and a first electrical contact on the second chip. At least a portion of the first electrical contact does not overlap with the first chip in a plan view.
1. A package, comprising:
a first chip stack including:
a first chip including first bonding structures;
a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures; and
a first electrical contact on the second chip, wherein at least a portion of the first electrical contact does not overlap with the first chip in a plan view;
a second chip stack adhering to the first chip stack and including:
a third chip including third bonding structures;
a fourth chip including fourth bonding structures facing the third bonding structures and bonded to the third bonding structures; and
a second electrical contact on the fourth chip, wherein at least a portion of the second electrical contact does not overlap with the third chip in the plan view, wherein the first chip and the third chip have a same first footprint, and wherein the second chip and the fourth chip have a same second footprint different than the first footprint.
2. The package of claim 1 , wherein the first electrical contact is located at a first side of the second chip.
3. The package of claim 1 , wherein, in a cross sectional view, a width of the first chip is less than a width of the second chip.
4. The package of claim 1 , further comprising:
a support substrate that supports the first chip stack and the second chip stack.
5. The package of claim 4 , wherein, in a cross sectional view, a width of the first chip is less than a width of the second chip, and a width of the third chip is less than a width of the fourth chip, and wherein the first electrical contact and the second electrical contact overlap one another in the plan view.
6. The package of claim 4 , wherein the first chip stack and the second chip stack are aligned with one another.
7. The package of claim 6 , wherein the portion of the second electrical contact does not overlap the first chip in the plan view.
8. The package of claim 4 , wherein the first chip stack and the second chip stack are offset from one another.
9. The package of claim 4 , further comprising:
a first bonding wire electrically connected to the first electrical contact; and
a second bonding wire electrically connected to the second electrical contact.
10. The package of claim 9 , wherein the first electrical contact and the second electrical contact overlap in the plan view.
11. The package of claim 1 , wherein the first chip or the second chip, or both, is a reconstituted chip.
12. The package of claim 1 , wherein the first chip stack and the second chip stack are offset from one another.
13. The package of claim 1 , wherein the first chip stack and the second chip stack are aligned with one another.
14. A package, comprising:
a first chip stack including:
a first chip including first bonding structures;
a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures;
a first electrical contact on the second chip, wherein at least a portion of the first electrical contact does not overlap with the first chip in a plan view, and wherein the first electrical contact is located at a first side of the second chip; and
a second electrical contact on the second chip and located at a second side of the second chip opposite the first side of the second chip.
15. The package of claim 14 , wherein at least a portion of the second electrical contact does not overlap with the first chip in the plan view.
16. A package, comprising:
a first chip stack including:
a first chip including first bonding structures;
a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures; and
a first electrical contact on the second chip, wherein the first electrical contact does not overlap with the first chip in a plan view; and
a second chip stack adhering to the first chip stack and including:
a third chip including third bonding structures;
a fourth chip including fourth bonding structures facing the third bonding structures and bonded to the third bonding structures; and
a second electrical contact on the fourth chip, wherein the second electrical contact does not overlap with the third chip in the plan view; and
a support substrate that supports the first chip stack and the second chip stack, wherein a width of the first chip is less than a width of the second chip, and a width of the third chip is less than a width of the fourth chip, and wherein the first electrical contact and the second electrical contact overlap one another in the plan view.
17. The package of claim 16 , wherein the first chip or the second chip, or both, is a reconstituted chip.
18. The package of claim 16 , wherein the first chip stack and the second chip stack are aligned with one another.
19. The package of claim 16 , wherein a portion of the second electrical contact does not overlap the first chip in the plan view.
20. The package of claim 16 , wherein the first chip stack and the second chip stack are offset from one another.