IP Library Granted Patent US 12,243,852
Granted Patent B2
US 12,243,852 · App. 18/353,343 · Granted Mar 4, 2025

Semiconductor package and manufacturing method thereof

Inventor: Akihito Sawanobori (Yokkaichi, JP)
Assignee: KIOXIA CORPORATION
H01L25/0657H01L21/4853H01L21/4857H01L21/565H01L23/3121H01L23/49822H01L23/552H01L24/48H01L2224/48227H01L2225/06506H01L2225/0651H01L2225/06537H01L2225/06562H01L2225/06582H01L2924/3025
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Quick Facts
Patent No.
US 12,243,852
App. No.
18/353,343
Granted
Mar 4, 2025
Kind
B2
Abstract

A semiconductor package according to one embodiment comprises a substrate. A semiconductor chip is provided on the substrate. A resin layer is configured to cover the semiconductor chip on the substrate. A metal film is configured to cover a surface and side surfaces of the resin layer. The metal film is a laminated film including first to fourth metal layers. The first metal layer is configured to cover the resin layer. The second metal layer includes a first metal material that is different from a material of the first metal layer. The third metal layer includes an alloy of the first metal material forming the second metal layer and a second metal material different from the first metal material. The fourth metal layer is configured to cover the second or third metal layer.

Claims (53)

1. A manufacturing method of a semiconductor package, comprising:

placing a semiconductor chip on a substrate;

covering the semiconductor chip with a resin layer;

covering a surface and side surfaces of the resin layer with a first metal layer;

depositing a second metal layer including a first metal material that is different from a material of the first metal layer at a temperature of 150 degrees or higher;

depositing a third metal layer including an alloy of the first metal material forming the second metal layer and a second metal material different from the first metal material; and

covering the second or third metal layer with a fourth metal layer, wherein

content of the second metal material included in the third metal layer is 1 to 20 atomic percent,

a grain size in the second metal layer is 0.10 μm or more,

a grain size in the third metal layer is less than 0.10 μm,

a total thickness of the second and third metal layers is in a range of 0.45 μm to 2.5 μm,

a resistance value of the second metal layer is lower than resistance values of the first, third, and fourth metal layers,

the second metal layer is provided on the first metal layer,

the third metal layer is provided on the second metal layer, and

the fourth metal layer is provided on the third metal layer.

2. The method of claim 1 , wherein

the third metal layer is deposited on the first metal layer,

the second metal layer is deposited on the third metal layer, and

the fourth metal layer is deposited on the second metal layer.

3. The method of claim 1 , further comprising depositing a fifth metal layer including an alloy of the first metal material and a third metal material different from the first metal material on the first metal layer, wherein

the second metal layer is provided on the fifth metal layer,

the third metal layer is provided on the second metal layer, and

the fourth metal layer is provided on the third metal layer.

4. The method of claim 3 , wherein a grain size in the second metal layer is larger than grain sizes in the third and fifth metal layers.

5. The method of claim 3 , wherein a resistance value of the second metal layer is lower than resistance values of the first and third to fifth metal layers.

6. The method of claim 1 , wherein a grain size in the second metal layer is larger than a grain size in the third metal layer.

7. The method of claim 1 , wherein at least the second metal layer is provided on a side surface of the substrate and is connected to a portion of a wire of the substrate.

8. The method of claim 1 , wherein

the first metal layer includes a metal material containing stainless steel, nickel, or titanium,

the second metal layer includes a metal material containing copper, nickel, or titanium, and

the third metal layer includes an alloy including copper, nickel, or titanium as a base material and at least one additional material selected from aluminum (Al), cobalt (Co), chromium (Cr), germanium (Ge), indium (In), magnesium (Mg), manganese (Mn), nickel (Ni), silicon (Si), tin (Sn), titanium (Ti), zinc (Zn), molybdenum (Mo), and iron (Fe), where the additional material is a material other than nickel in a case where the base material is nickel, and the additional material is a material other than titanium in a case where the base material is titanium.

9. A manufacturing method of a semiconductor package, comprising:

placing a semiconductor chip on a substrate;

covering the semiconductor chip with a resin layer,

covering a surface and side surfaces of the resin layer with a first metal layer;

depositing a second metal layer including a first metal material that is different from a material of the first metal layer;

depositing a third metal layer including an alloy of the first metal material forming the second metal layer and a second metal material different from the first metal material; and

covering the second or third metal layer with a fourth metal layer, wherein

the second metal material is 1 to 20 atomic percent of the third metal layer,

a grain size in the second metal layer is 0.10 μm or more,

a grain size in the third metal layer is less than 0.10 μm,

a total thickness of the second and third metal layers is in a range of 0.45 μm to 2.5 μm,

a resistance value of the second metal layer is lower than resistance values of the first, third, and fourth metal layers,

the second metal layer is provided on the first metal layer,

the third metal layer is provided on the second metal layer, and

the fourth metal layer is provided on the third metal layer.

10. The method of claim 9 , wherein a grain size in the second metal layer is larger than a grain size in the third metal layer.

11. The method of claim 9 , wherein a resistance value of the second metal layer is lower than resistance values of the first, third, and fourth metal layers.

12. The method of claim 9 , wherein at least the second metal layer is provided on a side surface of the substrate and is connected to a portion of a wire of the substrate.

13. The method of claim 9 , wherein

the first metal layer includes a metal material containing stainless steel, nickel, or titanium,

the second metal layer includes a metal material containing copper, nickel, or titanium, and

the third metal layer includes an alloy including copper, nickel, or titanium as a base material and at least one additional material selected from aluminum (Al), cobalt (Co), chromium (Cr), germanium (Ge), indium (In), magnesium (Mg), manganese (Mn), nickel (Ni), silicon (Si), tin (Sn), titanium (Ti), zinc (Zn), molybdenum (Mo), and iron (Fe), where the additional material is a material other than nickel in a case where the base material is nickel, and the additional material is a material other than titanium in a case where the base material is titanium.

Priority Claims (1)
JP 2020-017171 · Feb 4, 2020 · national
Continuity (2)
Division 17016594 · Sep 10, 2020
Related Publication 20230361084A1 · Nov 9, 2023
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