Semiconductor device and solid-state imaging sensor
A semiconductor device according to an aspect of the present technology includes a low-concentration N-type region, a first high-concentration N-type region and a second high-concentration N-type region that are stacked with the low-concentration N-type region interposed therein, a gate electrode that surrounds the low-concentration N-type region as viewed from a stacking direction, which is a direction in which the low-concentration N-type region, the first high-concentration N-type region, and the second high-concentration N-type region are stacked, a first insulating film placed between the gate electrode and the low-concentration N-type region, and a second insulating film placed between the gate electrode and the first high-concentration N-type region. The first high-concentration N-type region is connected to one of a source electrode and a drain electrode. The second high-concentration N-type region is connected to the other of the source electrode and the drain electrode.
1. A semiconductor device, comprising:
a low-concentration N-type region;
a first high-concentration N-type region and a second high-concentration N-type region that are stacked with the low-concentration N-type region interposed therein, and that have a higher concentration of impurity than the low-concentration N-type region;
a gate electrode that surrounds the low-concentration N-type region as viewed from a stacking direction which is a direction in which the low-concentration N-type region, the first high-concentration N-type region, and the second high-concentration N-type region are stacked;
a first insulating film placed between the gate electrode and the low-concentration N-type region; and
a second insulating film placed between the gate electrode and the first high-concentration N-type region, wherein
the first high-concentration N-type region is connected to a first one of a source electrode and a drain electrode; and
the second high-concentration N-type region is connected to a second one of the source electrode and the drain electrode,
wherein the first high-concentration N-type region includes a facing region that is a region facing the low-concentration N-type region with the gate electrode interposed therebetween,
wherein the semiconductor device further comprises a third insulating film placed between the facing region and the gate electrode, and
wherein a thickness of the second insulating film and a thickness of the third insulating film is thicker than a thickness of the first insulating film.
2. A semiconductor device, comprising:
a low-concentration N-type region;
a first high-concentration N-type region and a second high-concentration N-type region that are stacked with the low-concentration N-type region interposed therein, and that have a higher concentration of impurity than the low-concentration N-type region;
a gate electrode that surrounds the low-concentration N-type region as viewed from a stacking direction which is a direction in which the low-concentration N-type region, the first high-concentration N-type region, and the second high-concentration N-type region are stacked;
a first insulating film placed between the gate electrode and the low-concentration N-type region; and
a second insulating film placed between the gate electrode and the first high-concentration N-type region, wherein
the first high-concentration N-type region is connected to a first one of a source electrode and a drain electrode; and
the second high-concentration N-type region is connected to a second one of the source electrode and the drain electrode,
wherein the first high-concentration N-type region includes a facing region that is a region facing the low-concentration N-type region with the gate electrode interposed therebetween,
wherein the semiconductor device further comprises a third insulating film placed between the facing region and the gate electrode, and
wherein a thickness of the third insulating film is thicker than a thickness of the first insulating film and a thickness of the second insulating film.
3. The semiconductor device according to claim 1 , comprising
a plurality of the second high-concentration N-type regions and a plurality of the low-concentration N-type regions,
wherein a plurality of the second high-concentration N-type regions and a plurality of the low-concentration N-type regions are stacked in the first high-concentration N-type region.
4. The semiconductor device according to claim 1 , wherein
at least one of silicon oxide, silicon nitride, and hafnium oxide is used as a material of the first insulating film and the second insulating film.
5. The semiconductor device according to claim 1 , wherein
at least one of silicon oxide, silicon nitride, and hafnium oxide is used as a material of the third insulating film.
6. The semiconductor device according to claim 2 , wherein
at least one of silicon oxide, silicon nitride, and hafnium oxide is used as a material of the third insulating film.
7. The semiconductor device according to claim 1 , wherein
at least one of polycrystalline silicon, titanium nitride, copper, aluminum, and tungsten is used as a material of the gate electrode.
8. The semiconductor device according to claim 1 ,
wherein a concentration of impurity of the low-concentration N-type region is not higher than 10 keV/1E 18 (cm −2 ), and
wherein a concentration of impurity of the first high-concentration N-type region and the second high-concentration N-type region is not lower than 10 keV/1E 19 (cm −2 ).
9. The semiconductor device according to claim 1 , wherein a shape of the low-concentration N-type region is square as viewed from the stacking direction, and
wherein a shape of the gate electrode is square as viewed from the stacking direction.
10. The semiconductor device according to claim 1 , wherein a shape of the low-concentration N-type region is circular as viewed from the stacking direction, and
wherein a shape of the gate electrode is circular as viewed from the stacking direction.
11. A semiconductor device, comprising:
a low-concentration N-type region;
a first high-concentration N-type region and a second high-concentration N-type region that are stacked with the low-concentration N-type region interposed therein, and that have a higher concentration of impurity than the low-concentration N-type region;
a gate electrode that surrounds the low-concentration N-type region as viewed from a stacking direction which is a direction in which the low-concentration N-type region, the first high-concentration N-type region, and the second high-concentration N-type region are stacked;
a first insulating film placed between the gate electrode and the low-concentration N-type region; and
a second insulating film placed between the gate electrode and the first high-concentration N-type region, wherein
the first high-concentration N-type region is connected to a first one of a source electrode and a drain electrode; and
the second high-concentration N-type region is connected to a second one of the source electrode and the drain electrode,
wherein a face connected to the source electrode or the drain electrode of the first high-concentration N-type region, and a face connected to the source electrode or the drain electrode of the second high-concentration N-type region, are at a same height as viewed from a direction orthogonal to the stacking direction.
12. The semiconductor device according to claim 1 , wherein a face connected to the source electrode or the drain electrode of the first high-concentration N-type region, and a face connected to the source electrode or the drain electrode of the second high-concentration N-type region, are at different heights as viewed from a direction orthogonal to the stacking direction.
13. The semiconductor device according to claim 1 , wherein-the low-concentration N-type region has a portion not facing the gate electrode.
14. A solid-state imaging sensor, comprising:
a pixel circuit that is provided with an amplifying transistor, wherein the semiconductor device according to claim 1 is built into the amplifying transistor.
15. The semiconductor device according to claim 2 , comprising
a plurality of the second high-concentration N-type regions and a plurality of the low-concentration N-type regions,
wherein a plurality of the second high-concentration N-type regions and a plurality of the low-concentration N-type regions are stacked in the first high-concentration N-type region.
16. The semiconductor device according to claim 2 , wherein
at least one of silicon oxide, silicon nitride, and hafnium oxide is used as a material of the first insulating film and the second insulating film.
17. The semiconductor device according to claim 2 , wherein
at least one of polycrystalline silicon, titanium nitride, copper, aluminum, and tungsten is used as a material of the gate electrode.
18. The semiconductor device according to claim 2 ,
wherein a concentration of impurity of the low-concentration N-type region is not higher than 10 keV/1E 18 (cm −2 ), and
wherein a concentration of impurity of the first high-concentration N-type region and the second high-concentration N-type region is not lower than 10 keV/1E 19 (cm −2 ).
19. The semiconductor device according to claim 2 ,
wherein a shape of the low-concentration N-type region is square as viewed from the stacking direction, and
and wherein a shape of the gate electrode is square as viewed from the stacking direction.
20. The semiconductor device according to claim 2 , wherein a shape of the low-concentration N-type region is circular as viewed from the stacking direction, and
wherein a shape of the gate electrode is circular as viewed from the stacking direction.
21. The semiconductor device according to claim 2 , wherein a face connected to the source electrode or the drain electrode of the first high-concentration N-type region, and a face connected to the source electrode or the drain electrode of the second high-concentration N-type region, are at different heights as viewed from a direction orthogonal to the stacking direction.
22. The semiconductor device according to claim 2 , wherein the low-concentration N-type region has a portion not facing the gate electrode.
23. A solid-state imaging sensor, comprising:
a pixel circuit that is provided with an amplifying transistor, wherein the semiconductor device according to claim 2 is built into the amplifying transistor.
24. The semiconductor device according to claim 1 , wherein a face connected to the source electrode or the drain electrode of a first-high-concentration N-type region, and a face connected to the source electrode or the drain electrode of a second high-concentration N-type region, are at a same height as viewed from a direction orthogonal to the stacking direction.
25. The semiconductor device according to claim 2 , wherein a face connected to the source electrode or the drain electrode of a first-high-concentration N-type region, and a face connected to the source electrode or the drain electrode of a second high-concentration N-type region, are at a same height as viewed from a direction orthogonal to the stacking direction.
26. The semiconductor device according to claim 11 , comprising
a plurality of the second high-concentration N-type regions and a plurality of the low-concentration N-type regions,
wherein a plurality of the second high-concentration N-type regions and a plurality of the low-concentration N-type regions are stacked in the first high-concentration N-type region.
27. The semiconductor device according to claim 11 , wherein
at least one of silicon oxide, silicon nitride, and hafnium oxide is used as a material of the first insulating film and the second insulating film.