Semiconductor device having duty-cycle corrector
An apparatus according to some embodiments comprises: a first clock path including a first duty-cycle adjuster that adjusts a duty cycle of a first input clock signal, a second clock path including a second duty-cycle adjuster that adjusts a duty cycle of a second input clock signal having a different phase from the first input clock signal; and a control circuit configured to detect longest one or shortest one of first, second, third, and fourth time periods to generate a control signal. The first, second, third and fourth time periods are defined by phase differences between rising edges and falling edges of the first and second input clock signals.
1. An apparatus, comprising:
a first clock path including a first duty-cycle adjuster configured to adjust a duty-cycle of a first input clock signal;
a second clock path including a second duty-cycle adjuster configured to adjust a duty-cycle of a second input clock signal having a different phase in 90 degrees from the first input clock signal; and
a control circuit configured to detect longest one of first, second, third, and fourth time periods to generate a control signal, wherein the first time period is defined by a phase difference between a rising edge of the first input clock signal and a rising edge of the second input clock signal, the second time period is defined by a phase difference between the rising edge of the second input clock signal and a falling edge of the first input clock signal, the third time period is defined by a phase difference between the falling edge of the first input clock signal and a falling edge of the second input clock signal, and the fourth time period is defined by a phase difference between the falling edge of the second input clock signal and the rising edge of the first input clock signal.
2. The apparatus as claimed in claim 1 , wherein the first and second duty-cycle adjusters are configured to adjust the rising and falling edges of the first and second input clock signals, respectively, responsive to the control signal.
3. The apparatus as claimed in claim 1 , wherein the control signal includes a first control signal that controls the rising edge of the first input clock signal, a second control signal that controls the falling edge of the first input clock signal, a third control signal that controls the rising edge of the second input clock signal, and a fourth control signal that controls the falling edge of the second input clock signal.
4. The apparatus as claimed in claim 1 , wherein the control circuit is configured to, if the first time period is the longest one, increase a delay of the rising edge of the first input clock signal or decrease a delay of the rising edge of the second input clock signal.
5. The apparatus as claimed in claim 1 ,
wherein the first clock path further includes a first phase splitter configured to generate a first output clock signal and a third output clock signal having a different phase in 180 degrees from the first output clock signal, and
wherein the second clock path further includes a second phase splitter configured to generate a second output clock signal and a fourth output clock signal having a different phase in 180 degrees from the second output clock signal.
6. The apparatus as claimed in claim 5 , wherein the control circuit includes:
a first duty-cycle detector configured to compare a duty-cycle of the first output clock signal with a duty-cycle of the third output clock signal;
a second duty-cycle detector configured to compare a duty-cycle of the second output clock signal with a duty-cycle of the fourth output clock signal; and
a third duty-cycle detector configured to detect phases among the first, second, third, and fourth output clock signals.
7. The apparatus as claimed in claim 6 , wherein the control circuit is configured to generate the control signal responsive to output signals of the first, second, and third duty-cycle detectors.
8. An apparatus, comprising:
a first clock path including a first duty-cycle adjuster configured to adjust a duty-cycle of a first input clock signal;
a second clock path including a second duty-cycle adjuster configured to adjust a duty-cycle of a second input clock signal having a different phase in 90 degrees from the first input clock signal; and
a control circuit configured to detect shortest one of first, second, third, and fourth time periods to generate a control signal, wherein the first time period is defined by a phase difference between a rising edge of the first input clock signal and a rising edge of the second input clock signal, the second time period is defined by a phase difference between the rising edge of the second input clock signal and a falling edge of the first input clock signal, the third time period is defined by a phase difference between the falling edge of the first input clock signal and a falling edge of the second input clock signal, and the fourth time period is defined by a phase difference between the falling edge of the second input clock signal and the rising edge of the first input clock signal.
9. The apparatus as claimed in claim 8 , wherein the first and second duty-cycle adjusters are configured to adjust the rising and falling edges of the first and second input clock signals, respectively, responsive to the control signal.
10. The apparatus as claimed in claim 8 , wherein the control signal includes a first control signal that controls the rising edge of the first input clock signal, a second control signal that controls the falling edge of the first input clock signal, a third control signal that controls the rising edge of the second input clock signal, and a fourth control signal that controls the falling edge of the second input clock signal.
11. The apparatus as claimed in claim 8 , wherein the control circuit is configured to, if the first time period is the shortest one, decrease a delay of the rising edge of the first input clock signal or increase a delay of the rising edge of the second input clock signal.
12. The apparatus as claimed in claim 8 ,
wherein the first clock path further includes a first phase splitter configured to generate a first output clock signal and a third output clock signal having a different phase in 180 degrees from the first output clock signal, and
wherein the second clock path further includes a second phase splitter configured to generate a second output clock signal and a fourth output clock signal having a different phase in 180 degrees from the second output clock signal.
13. The apparatus as claimed in claim 12 , wherein the control circuit includes:
a first duty-cycle detector configured to compare a duty-cycle of the first output clock signal with a duty-cycle of the third output clock signal;
a second duty-cycle detector configured to compare a duty-cycle of the second output clock signal with a duty-cycle of the fourth output clock signal; and
a third duty-cycle detector configured to detect phases among the first, second, third, and fourth output clock signals.
14. The apparatus as claimed in claim 13 , wherein the control circuit is configured to generate the control signal responsive to output signals of the first, second, and third duty-cycle detectors.
15. An apparatus, comprising:
a first clock path including a first duty-cycle adjuster of a first input clock signal;
a second clock path including a second duty-cycle adjuster of a second input clock signal having a different phase from the first input clock signal; and
a control circuit configured to:
detect longest one and shortest one of first, second, third, and fourth time periods to generate a control signal, wherein the first time period is defined by a phase difference between a rising edge of the first input clock signal and a rising edge of the second input clock signal, the second time period is defined by a phase difference between the rising edge of the second input clock signal and a falling edge of the first input clock signal, the third time period is defined by a phase difference between the falling edge of the first input clock signal and a falling edge of the second input clock signal, and the fourth time period is defined by a phase difference between the falling edge of the second input clock signal and the rising edge of the first input clock signal;
if the first time period is the longest one, increase a delay of the rising edge of the first input clock signal or decrease a delay of the rising edge of the second input clock signal; and
if the first time period is the shortest one, decrease a delay of the rising edge of the first input clock signal or increase a delay of the rising edge of the second input clock signal.
16. The apparatus as claimed in claim 15 , wherein the first and second duty-cycle adjusters are configured to adjust the rising and falling edges of the first and second input clock signals, respectively, responsive to the control signal.
17. The apparatus as claimed in claim 15 , wherein the control signal includes a first control signal that controls the rising edge of the first input clock signal, a second control signal that controls the falling edge of the first input clock signal, a third control signal that controls the rising edge of the second input clock signal, and a fourth control signal that controls the falling edge of the second input clock signal.
18. The apparatus as claimed in claim 15 ,
wherein the first clock path further includes a first phase splitter configured to generate a first output clock signal and a third output clock signal having a different phase in 180 degrees from the first output clock signal, and
wherein the second clock path further includes a second phase splitter configured to generate a second output clock signal and a fourth output clock signal having a different phase in 180 degrees from the second output clock signal.
19. The apparatus as claimed in claim 18 , wherein the control circuit includes:
a first duty-cycle detector configured to compare a duty-cycle of the first output clock signal with a duty-cycle of the third output clock signal;
a second duty-cycle detector configured to compare a duty-cycle of the second output clock signal with a duty-cycle of the fourth output clock signal; and
a third duty-cycle detector configured to detect phases among the first, second, third, and fourth output clock signals.
20. The apparatus as claimed in claim 19 , wherein the control circuit is configured to generate the control signal responsive to output signals of the first, second, and third duty-cycle detectors.