IP Library › Granted Patent US 12,245,428
Granted Patent B2
US 12,245,428 · App. 17/575,418 · Granted Mar 4, 2025

3D AND flash memory device and method of fabricating the same

Inventors: Hang-Ting Lue (Hsinchu, TW); Chia-Jung Chiu (Hsinchu County, TW); Teng-Hao Yeh (Hsinchu County, TW); Guan-Ru Lee (Hsinchu, TW)
Assignee: MACRONIX International Co., Ltd.
H10B43/27H10B41/10H10B41/27H10B43/10H01L21/786
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Quick Facts
Patent No.
US 12,245,428
App. No.
17/575,418
Granted
Mar 4, 2025
Kind
B2
Abstract

A three-dimensional AND flash memory device includes a gate stack structure, a charge storage structure, a first conductive pillar and a second conductive pillar, an insulating pillar, and a channel pillar. The gate stack structure includes gate layers and insulating layers stacked alternately with each other. The first and second conductive pillars extend through the gate stack structure. The channel pillar extends through the gate stack structure. The charge storage structure is disposed between the gate stack structure and the channel pillar. The channel pillar includes: a first part and a second part connected each other. The first part is located between the charge storage structure and the insulating pillar. The second part includes a first region electrically connected to the first conductive pillar, and a second region electrically connected to the second conductive pillar. A curvature of the first part is smaller than a curvature of the second part.

Claims (29)

1. A three-dimensional AND flash memory device, comprising:

a gate stack structure located on a surface of a dielectric substrate, wherein the gate stack structure comprises a plurality of gate layers and a plurality of insulating layers alternately stacked with each other;

a first conductive pillar and a second conductive pillar extending through the gate stack structure;

an insulating pillar separating the first conductive pillar and the second conductive pillar;

a channel pillar extending through the gate stack structure; and

a charge storage structure disposed between the gate stack structure and the channel pillar, wherein the channel pillar, the first conductive pillar, the second conductive pillar and the insulating pillar are enclosed by and in the charge storage structure;

wherein the channel pillar comprises:

a first part located between the charge storage structure and the insulating pillar; and

a second part comprising a first region electrically connected to the first conductive pillar and a second region electrically connected to the second conductive pillar,

wherein the first part is connected to the second part, and a curvature of the first part is smaller than a curvature of the second part,

wherein the insulating pillar comprises a first sidewall connected to the first part and a second sidewall connected to the first conductive pillar and the second conductive pillar, and the first sidewall is connected to the second sidewall,

wherein a projection of the insulating pillar on the surface of the dielectric substrate has an entirely elliptical profile.

2. The three-dimensional AND flash memory device according to claim 1 , wherein a projection of the channel pillar on the surface of the dielectric substrate has an elliptical profile.

3. The three-dimensional AND flash memory device according to claim 2 , wherein the first conductive pillar and the second conductive pillar are disposed on a long axis of the elliptical profile.

4. The three-dimensional AND flash memory device according to claim 1 , wherein the channel pillar is conformal with and in contact with a tunneling layer of the charge storage structure.

5. The three-dimensional AND flash memory device according to claim 4 , wherein the first conductive pillar and the second conductive pillar are located between the insulating pillar and the second part of the channel pillar.

6. The three-dimensional AND flash memory device according to claim 5 , wherein volumes of the first conductive pillar and the conductive pillar are substantially the same as volumes of the spaces between the insulating pillar and the second portion of the channel pillar.

7. The three-dimensional AND flash memory device according to claim 1 , wherein an inner sidewall of the channel pillar is conformal with an outer sidewall of the insulating pillar.

8. The three-dimensional AND flash memory device according to claim 7 , wherein the first conductive pillar and the second conductive pillar are located between the second part of the channel pillar and the charge storage structure.

9. The three-dimensional AND flash memory device according to claim 8 , wherein volumes of the first conductive pillar and the conductive pillar are substantially the same as volumes of the spaces between the insulating pillar and the charge storage structure.

10. A three-dimensional AND flash memory device, comprising:

a gate stack structure located on a surface of a dielectric substrate, wherein the gate stack structure comprises a plurality of gate layers and a plurality of insulating layers alternately stacked with each other;

a channel pillar extending through the gate stack structure, wherein a projection of the channel pillar on the surface of the dielectric substrate has an elliptical profile;

a charge storage structure located between the gate layers and the channel pillar;

an insulating pillar located in the channel pillar; and

a source pillar and a drain pillar disposed on a long axis of the elliptical profile and extending through the gate stack structure, surrounded by the charge storage structure and separated by the insulating pillar, and electrically connected to the channel pillar,

wherein the insulating pillar comprises a first sidewall connected to the channel pillar and a second sidewall connected to the source pillar and the drain pillar, and the first sidewall is connected to the second sidewall,

wherein a projection of the insulating pillar on the surface of the dielectric substrate has an entirely elliptical profile.

11. The three-dimensional AND flash memory device according to claim 10 , wherein a projection of the charge storage structure on the surface of the dielectric substrate has an entirely elliptical profile.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2022
From: LUE, HANG-TING; CHIU, CHIA-JUNG; YEH, TENG-HAO; LEE, GUAN-RU
To: MACRONIX INTERNATIONAL CO., LTD.
Reel/Frame 058717/0161 →
Continuity (1)
Related Publication 20230225126A1 · Jul 13, 2023
References Cited (4)
US 9589979B2 · Hong · 2017 [cited by applicant]
US 20140264897A1 · Chiu et al. · 2014 [cited by applicant]
H.-T. Lue et al., “3D AND: A 3D Stackable Flash Memory Architecture to Realize High-Density and Fast-Read 3D NOR Flash and Storage-Class Memory,” 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, C… [cited by examiner]
“Notice of allowance of Taiwan Counterpart Application”, issued on Jun. 20, 2023, p. 1-p. 3. [cited by applicant]