Interconnection for a memory array and methods for forming the same
Semiconductor structure and methods of forming the same are provided. An exemplary method includes providing a substrate having a first region and a second region, forming an array of memory cells over the first region of the substrate, and forming a memory-level dielectric layer around the array of memory cells. Each of the memory cells includes, from bottom to top, a bottom electrode, a memory material layer stack, and a top electrode. The exemplary method also includes forming a metal line directly interfacing a respective row of top electrodes of the array of memory cells. The metal line also directly interfaces a top surface of the memory-level dielectric layer.
1. A method of manufacturing a memory array device, comprising:
providing a substrate, wherein the substrate has a first region and a second region; forming an array of memory cells over the first region of the substrate, wherein each of the memory cells includes, from bottom to top, a bottom electrode, a memory material layer stack, and a top electrode;
forming a memory-level dielectric layer around the array of memory cells; and
forming elongated cavities in the memory-level dielectric layer, wherein the elongated cavities expose the top electrodes of the array of memory cells;
depositing a metallic material in the elongated cavities;
forming a metal line, wherein a bottom surface of the metal line has a continuously flat portion, wherein the continuously flat portion of the bottom surface directly interfaces a respective row of top electrodes of the array of memory cells, wherein the metal line also directly interfaces a top surface of the memory-level dielectric layer.
2. The method of claim 1 , wherein the first region is a memory region and the second region is a logic region, and wherein the metal line extends into the second region.
3. The method of claim 2 , wherein the metal line has a larger thickness in the second region than in the first region.
4. The method of claim 1 , further comprising:
forming a sacrificial dielectric layer over the first and second regions, wherein the sacrificial dielectric layer covers the array of memory cells;
planarizing the top electrodes of the array of memory cells; and
removing the sacrificial dielectric layer from the first and second regions.
5. The method of claim 4 , further comprising:
forming a dielectric encapsulation structure prior to the forming of the sacrificial dielectric layer,
wherein the dielectric encapsulation structure covers the array of memory cells, and wherein the planarizing of the top electrodes of the array of memory cells exposes the top electrodes from the sacrificial dielectric layer.
6. The method of claim 1 , wherein an interface between the metal line and the respective row of the top electrodes is within a horizontal plane including the top surface of the memory-level dielectric layer.
7. The method of claim 1 , wherein the forming of the metal line includes:
removing portions of the metallic material from above the memory-level dielectric layer, wherein remaining portions of the metallic material comprise the metal line.
8. The method of claim 7 , wherein the remaining portions of the metallic material also comprise a metal via in the second region.
9. The method of claim 1 , wherein the forming of the memory-level dielectric layer includes:
depositing a dielectric material over the first and second regions, wherein a first portion of the dielectric material in the first region is higher than a second portion of the dielectric material in the second region; and
recessing the first portion of the dielectric material in an etching process, while the second portion of the dielectric material remains intact.
10. The method of claim 9 , wherein after the recessing of the first portion of the dielectric material, the first portion of the dielectric material is lower than the second portion of the dielectric material.
11. A method, comprising:
forming an array of memory cells over a substrate, each of the memory cells including a bottom electrode, a magnetic tunnel junction, and a top electrode;
depositing an encapsulation layer covering the array of memory cells;
performing a planarization process, thereby exposing top electrodes of the array of memory cells from the encapsulation layer;
depositing a dielectric layer covering the top electrodes and the encapsulation layer;
forming a cavity in the dielectric layer, thereby exposing a row of the top electrodes; and
forming a metal line in the cavity, the metal line having a portion of a bottom surface that is continuously flat and physically contacting the row of the top electrodes.
12. The method of claim 11 , wherein a bottom surface of the cavity has a portion offset from the encapsulation layer, and wherein the portion of the bottom surface of the cavity is below a top surface of the top electrodes.
13. The method of claim 11 , wherein a bottom surface of the metal line has a portion offset from the array of memory cells, and wherein the portion of the bottom surface of the metal line is below a bottom surface of the top electrodes.
14. The method of claim 11 , further comprising:
forming a via landing on the metal line, wherein the via is offset from the array of memory cells.
15. The method of claim 14 , wherein a portion of the metal line where the via lands is thicker than another portion of the metal line directly above the row of the top electrodes.
16. The method of claim 11 , further comprising:
forming an anti-reflection layer above the dielectric layer; and
performing a maskless etching process, such that a portion of the dielectric layer directly above the array of memory cells is recessed, while another portion of the dielectric layer offset from the array of memory cells remains intact under the anti-reflection layer.
17. A method, comprising: forming a dielectric cap layer over a substrate, the substrate having a memory region and a logic region, the dielectric cap layer extending from the memory region to the logic region;
forming a plurality of memory cells overlying the dielectric cap layer in the memory region, each of the memory cells including a top electrode;
forming dielectric spacers on sidewalls of the memory cells;
depositing an encapsulation layer covering the dielectric spacers and the top electrodes of the memory cells;
performing an etching process to expose the dielectric cap layer in the logic region, while the encapsulation layer in the memory region remains;
removing a portion of the encapsulation layer to expose the top electrodes of the memory cells;
depositing a dielectric layer in physical contact with the top electrodes of the memory cells in the memory region and the dielectric cap layer in the logic region, the dielectric layer covering the encapsulation layer;
forming elongated cavities in the memory-level dielectric layer, wherein the elongated cavities expose the top electrodes of the array of memory cells;
depositing a metallic material in the elongated cavities;
and forming a metal line in the elongated cavities, the metalline has a portion of a bottom surface that is continuously flat and physically contacting the top electrodes of the memory cells.
18. The method of claim 17 , wherein after the depositing of the dielectric layer, a top surface of the dielectric layer is non-flat.
19. The method of claim 17 , wherein after a bottom surface of the elongated cavities is lower in the logic region than in the memory region.
20. The method of claim 17 , wherein the forming of the elongated cavities includes etching the dielectric layer in a maskless etching process.