IP Library › Granted Patent US 12,248,382
Granted Patent B2
US 12,248,382 · App. 18/100,943 · Granted Mar 11, 2025

Data center environment architecture including system under test component analysis for use when performing test automation orchestration

Inventor: Vijay Narayana Reddy Halaharvi (Round Rock, TX)
Assignee: Dell Products L.P.
G06F11/2294G06F11/0709
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Quick Facts
Patent No.
US 12,248,382
App. No.
18/100,943
Granted
Mar 11, 2025
Kind
B2
Abstract

A system, method, and computer-readable medium for performing a data center management and monitoring operation. The data center management and monitoring operation includes: receiving a plurality of system under test (SUT) test plans, each SUT test plan comprising a plurality of SUT test cases; analyzing the plurality of SUT test cases, the analyzing comprising generating a phase component resolution score for each of the plurality of SUT test cases; generating a continuous schedule for the SUT test plan, the generating the continuous schedule taking into account the phase component resolution score for each of the plurality of SUT test cases; and, continuously orchestrating the SUT test plan based upon the continuous schedule for the SUT test plan.

Claims (44)

1. A computer-implementable method for performing a data center management and monitoring operation, comprising:

receiving a plurality of system under test (SUT) test plans, each SUT test plan of the plurality of system under test (SUT) test plans comprising a plurality of SUT test cases, each of the plurality of SUT test cases being associated with a component of a data center asset contained within a data center;

analyzing the plurality of SUT test cases, the analyzing comprising generating a phase component resolution score for each of the plurality of SUT test cases, the phase component resolution score for each of the plurality of SUT test cases providing a second order analysis for prioritizing execution of test cases;

generating a continuous schedule for the plurality of SUT test plans, the generating the continuous schedule for the plurality of SUT test plans taking into account the phase component resolution score for each of the plurality of SUT test cases, the continuous schedule for the plurality of SUT test plans being regularly updated based upon one or both of new priorities and updated constraints;

continuously orchestrating the plurality of SUT test plans based upon the continuous schedule for the plurality of SUT test plans; and,

applying each of the plurality of SUT test cases to the associated component of the data center asset contained within the data center based upon the continuously orchestrating the plurality of SUT test plans; and

wherein the phase component resolution score for each of the plurality of SUT test cases is based upon one or more test case phase scores associated with each of the plurality of SUT test cases;

the one or more test case phase scores associated with each of the plurality of SUT test cases includes a submit to verify phase score and a verify to close phase score, and,

the phase component resolution scores for each of the plurality of SUT test cases for a submit to verify phase and a verify to close phase are combined to generate an overall phase component analysis score.

2. The method of claim 1 , wherein:

the analyzing ranks the plurality of SUT test cases using the phase component resolution scores for each of the plurality of SUT test cases.

3. The method of claim 1 , further comprising:

presenting a phase component resolution visual representation for a plurality of phase component resolution scores for a plurality of SUT test case components, the visual representation providing a visual indication of phase component analysis results.

4. A system comprising:

a processor;

a data bus coupled to the processor;

a data center asset client module; and,

a non-transitory, computer-readable storage medium embodying computer program code, the non-transitory, computer-readable storage medium being coupled to the data bus, the computer program code interacting with a plurality of computer operations and comprising instructions executable by the processor and configured for:

receiving a plurality of system under test (SUT) test plans, each SUT test plan of the plurality of SUT test plans comprising a plurality of SUT test cases, each of the plurality of SUT test cases being associated with a component of a data center asset contained within a data center;

analyzing the plurality of SUT test cases, the analyzing comprising generating a phase component resolution score for each of the plurality of SUT test cases, the phase component resolution score for each of the plurality of SUT test cases providing a second order analysis for prioritizing execution of test cases;

generating a continuous schedule for the plurality of SUT test plans, the generating the continuous schedule for the plurality of SUT test plans taking into account the phase component resolution score for each of the plurality of SUT test cases, the continuous schedule for the plurality of SUT test plans being regularly updated based upon one or both of new priorities and updated constraints;

continuously orchestrating the plurality of SUT test plans based upon the continuous schedule for the plurality of SUT test plans; and,

applying each of the plurality of SUT test cases to the associated component of the data center asset contained within the data center based upon the continuously orchestrating the plurality of SUT test plans; and

wherein the phase component resolution score for each of the plurality of SUT test cases is based upon one or more test case phase scores associated with each of the plurality of SUT test cases;

the one or more test case phase scores associated with each of the plurality of SUT test cases includes a submit to verify phase score and a verify to close phase score, and,

the phase component resolution scores for each of the plurality of SUT test cases for a submit to verify phase and a verify to close phase are combined to generate an overall phase component analysis score.

5. The system of claim 4 , wherein:

the analyzing ranks the plurality of SUT test cases using the phase component resolution scores for each of the plurality of SUT test cases.

6. The system of claim 4 , wherein the instructions executable by the processor are further configured for:

presenting a phase component resolution visual representation for a plurality of phase component resolution scores for a plurality of SUT test case components, the visual representation providing a visual indication of phase component analysis results.

7. A non-transitory, computer-readable storage medium embodying computer program code, the computer program code comprising computer executable instructions configured for:

receiving a plurality of system under test (SUT) test plans, each SUT test plan of the plurality of system under test (SUT) test plans comprising a plurality of SUT test cases, each of the plurality of SUT test cases being associated with a component of a data center asset contained within a data center;

analyzing the plurality of SUT test cases, the analyzing comprising generating a phase component resolution score for each of the plurality of SUT test cases, the phase component resolution score for each of the plurality of SUT test cases providing a second order analysis for prioritizing execution of test cases;

generating a continuous schedule for the plurality of SUT test plans, the generating the continuous schedule for the plurality of SUT test plans taking into account the phase component resolution score for each of the plurality of SUT test cases, the continuous schedule for the plurality of SUT test plans being regularly updated based upon one or both of new priorities and updated constraints;

continuously orchestrating the plurality of SUT test plans based upon the continuous schedule for the plurality of SUT test plans; and,

applying each of the plurality of SUT test cases to the associated component of the data center asset contained within the data center based upon the continuously orchestrating the plurality of SUT test plans; and wherein the phase component resolution score for each of the plurality of SUT test cases is based upon one or more test case phase scores associated with each of the plurality of SUT test cases;

the one or more test case phase scores associated with each of the plurality of SUT test cases includes a submit to verify phase score and a verify to close phase score, and,

the phase component resolution scores for each of the plurality of SUT test cases for a submit to verify phase and a verify to close phase are combined to generate an overall phase component analysis score.

8. The non-transitory, computer-readable storage medium of claim 7 , wherein:

the analyzing ranks the plurality of SUT test cases using the phase component resolution scores for each of the plurality of SUT test cases.

9. The non-transitory, computer-readable storage medium of claim 7 , wherein the computer executable instructions are further configured for:

presenting a phase component resolution visual representation for a plurality of phase component resolution scores for a plurality of SUT test case components, the visual representation providing a visual indication of phase component analysis results.

10. The non-transitory, computer-readable storage medium of claim 7 , wherein: the computer executable instructions are deployable to a client system from a server system at a remote location.

11. The non-transitory, computer-readable storage medium of claim 7 , wherein: the computer executable instructions are provided by a service provider to a user on an on-demand basis.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2023
From: HALAHARVI, VIJAY NARAYANA REDDY
To: DELL PRODUCTS L.P.
Reel/Frame 062472/0662 →
Continuity (1)
Related Publication 20240248821A1 · Jul 25, 2024
References Cited (28)
US 9063673B2 · Weigert et al. · 2015 [cited by applicant]
US 10621078B2 · Salame · 2020 [cited by applicant]
US 12072790B1 · Pearson · 2024 [cited by applicant]
US 20040143819A1 · Cheng et al. · 2004 [cited by applicant]
US 20070220341A1 · Apostoloiu · 2007 [cited by examiner]
US 20080120521A1 · Poisson et al. · 2008 [cited by applicant]
US 20130117611A1 · Chakraborty et al. · 2013 [cited by applicant]
US 20140130014A1 · Jensen et al. · 2014 [cited by applicant]
US 20140380277A1 · Bhagavatula · 2014 [cited by examiner]
US 20150261657A1 · Kommineni et al. · 2015 [cited by applicant]
US 20160162392A1 · Hu et al. · 2016 [cited by applicant]
US 20180089071A1 · Keskitalo et al. · 2018 [cited by applicant]
US 20180307583A1 · Yang · 2018 [cited by examiner]
US 20190065345A1 · Patel et al. · 2019 [cited by applicant]
US 20190065353A1 · Tammariello et al. · 2019 [cited by applicant]
US 20200028772A1 · Laslau · 2020 [cited by examiner]
US 20200057712A1 · Mawson · 2020 [cited by examiner]
US 20220147438A1 · Gadagi · 2022 [cited by applicant]
US 20220179777A1 · Bhat · 2022 [cited by examiner]
US 20220188215A1 · Goswami · 2022 [cited by applicant]
US 20230082606A1 · Jebbar · 2023 [cited by examiner]
US 20230350791A1 · Kadirvel · 2023 [cited by examiner]
CN 102902622A · 2013 [cited by examiner]
WO 2008039964A1 · 2008 [cited by applicant]
Z. He, Z. Peng and P. Eles, “Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment,” 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, Patra… [cited by examiner]
Aneshvar, M., Mohammadi-ivatloo, B., Zare, K., Abapour, M., Asadi, S., & Anvari-moghaddam, A. (2021). Chance-constrained scheduling of hybrid microgrids under transactive energy control. International Journal of Energy … [cited by examiner]
Gerald D. Everett; Raymond McLeod, “Test Planning,” in Software Testing: Testing Across the Entire Software Development Life Cycle , IEEE, 2007, pp. 79-92 (Year: 2007). [cited by examiner]
List of Patents or Applications Treated as Related, Jan. 2023. [cited by applicant]
Cited By (1)
US 12,580,840