IP Library › Granted Patent US 12,248,416
Granted Patent B2
US 12,248,416 · App. 18/655,386 · Granted Mar 11, 2025

Programmable user-defined peripheral-bus device implementation using data-plane accelerator (DPA)

Inventors: Daniel Marcovitch (Yokneam Illit, IL); Eliav Bar-Ilan (Or Akiva, IL); Ran Avraham Koren (Beijing, CN); Liran Liss (Atzmon-Segev, IL); Oren Duer (Kochav Yair, IL); Shahaf Shuler (Kibbutz Lochamei Hagetaot, IL)
Assignee: Mellanox Technologies, Ltd
G06F13/28G06F13/4221G06F2213/0024
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Quick Facts
Patent No.
US 12,248,416
App. No.
18/655,386
Granted
Mar 11, 2025
Kind
B2
Abstract

A network adapter includes a network interface, a bus interface, a hardware-implemented data-path and a programmable Data-Plane Accelerator (DPA). The network interface is to communicate with a network. The bus interface is to communicate with an external device over a peripheral bus. The hardware-implemented data-path includes a plurality of packet-processing engines to process data units exchanged between the network and the external device. The DPA is to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path.

Claims (78)

1. A network adapter, comprising:

a network interface, to communicate with a network;

a bus interface, to communicate with an external device over a peripheral bus;

a hardware-implemented data-path, comprising a plurality of packet-processing engines to process data units exchanged between the network and the external device, the packet-processing engines including an address-translation engine to translate between virtual addresses in a first address space and addresses assigned to the data units in a second address space; and

a programmable Data-Plane Accelerator (DPA), to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path, including re-using the address-translation engine to translate between virtual addresses in a third address space and addresses assigned to UDPD data units associated with the UDPD in a fourth address space.

2. The network adapter according to claim 1 , wherein the UDPD is one of:

a network adapter;

a storage device;

a Graphics Processing Unit (GPU); and

a Field Programmable Gate Array (FPGA).

3. The network adapter according to claim 1 , wherein:

in processing the data units, the data-path is to communicate over the peripheral bus with a network-adapter driver running on the external device; and

in processing the transactions issued to the UDPD, the DPA is to communicate over the peripheral bus with a UDPD driver running on the external device.

4. A network adapter, comprising:

a network interface, to communicate with a network;

a bus interface, to communicate with an external device over a peripheral bus;

a hardware-implemented data-path, comprising a plurality of packet-processing engines to process data units exchanged between the network and the external device, the packet-processing engines including an interrupt-moderation engine to throttle a rate of interrupts that indicate completions of the data units; and

a programmable Data-Plane Accelerator (DPA), to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path, including re-using the interrupt-moderation engine to throttle a rate of interrupts that indicate completions of the UDPD data units.

5. The network adapter according to claim 4 , wherein the UDPD is one of:

a network adapter;

a storage device;

a Graphics Processing Unit (GPU); and

a Field Programmable Gate Array (FPGA).

6. The network adapter according to claim 4 , wherein:

in processing the data units, the data-path is to communicate over the peripheral bus with a network-adapter driver running on the external device; and

in processing the transactions issued to the UDPD, the DPA is to communicate over the peripheral bus with a UDPD driver running on the external device.

7. A network adapter, comprising:

a network interface, to communicate with a network;

a bus interface, to communicate with an external device over a peripheral bus;

a hardware-implemented data-path, comprising a plurality of packet-processing engines to process data units exchanged between the network and the external device, the packet-processing engines including a doorbell-aggregation engine to coalesce doorbells relating to the data units; and

a programmable Data-Plane Accelerator (DPA), to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path, including re-using the doorbell-aggregation engine to coalesce doorbells relating to UDPD data units associated with the UDPD.

8. The network adapter according to claim 7 , wherein the UDPD is one of:

a network adapter;

a storage device;

a Graphics Processing Unit (GPU); and

a Field Programmable Gate Array (FPGA).

9. The network adapter according to claim 7 , wherein:

in processing the data units, the data-path is to communicate over the peripheral bus with a network-adapter driver running on the external device; and

in processing the transactions issued to the UDPD, the DPA is to communicate over the peripheral bus with a UDPD driver running on the external device.

10. A method in a network adapter, the method comprising:

communicating with a network;

communicating with an external device over a peripheral bus;

using a hardware-implemented data-path that includes a plurality of packet-processing engines, processing data units exchanged between the network and the external device, including, by a hardware-implemented address-translation engine in the data-path, translating between virtual addresses in a first address space and addresses assigned to the communication data units in a second address space; and

using a programmable Data-Plane Accelerator (DPA), exposing on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), running user-programmable logic that implements the UDPD, and processing transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path, including re-using the address-translation engine by translating between virtual addresses in a third address space and addresses assigned to UDPD data units associated with the UDPD in a fourth address space.

11. The method according to claim 10 , wherein the UDPD is one of:

a network adapter;

a storage device;

a Graphics Processing Unit (GPU); and

a Field Programmable Gate Array (FPGA).

12. The method according to claim 10 , wherein:

processing the data units comprises communicating over the peripheral bus with a network-adapter driver running on the external device; and

processing the transactions issued to the UDPD comprises communicating over the peripheral bus with a UDPD driver running on the external device.

13. A method in a network adapter, the method comprising:

communicating with a network;

communicating with an external device over a peripheral bus;

using a hardware-implemented data-path that includes a plurality of packet-processing engines, processing data units exchanged between the network and the external device, including, by a hardware-implemented interrupt-moderation engine in the data-path, throttling a rate of interrupts that indicate completions of the data units; and

using a programmable Data-Plane Accelerator (DPA), exposing on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), running user-programmable logic that implements the UDPD, and processing transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path, including re-using the interrupt-moderation engine by throttling a rate of interrupts that indicate the completions of the UDPD data units.

14. The method according to claim 13 , wherein the UDPD is one of:

a network adapter;

a storage device;

a Graphics Processing Unit (GPU); and

a Field Programmable Gate Array (FPGA).

15. The method according to claim 13 , wherein:

processing the data units comprises communicating over the peripheral bus with a network-adapter driver running on the external device; and

processing the transactions issued to the UDPD comprises communicating over the peripheral bus with a UDPD driver running on the external device.

16. A method in a network adapter, the method comprising:

communicating with a network;

communicating with an external device over a peripheral bus;

using a hardware-implemented data-path that includes a plurality of packet-processing engines, processing data units exchanged between the network and the external device, including, by a doorbell-aggregation engine in the data-path, coalescing doorbells relating to the data units; and

using a programmable Data-Plane Accelerator (DPA), exposing on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), running user-programmable logic that implements the UDPD, and processing transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path, including re-using the doorbell-aggregation engine by coalescing doorbells relating to UDPD data units associated with the UDPD.

17. The method according to claim 16 , wherein the UDPD is one of:

a network adapter;

a storage device;

a Graphics Processing Unit (GPU); and

a Field Programmable Gate Array (FPGA).

18. The method according to claim 16 , wherein:

processing the data units comprises communicating over the peripheral bus with a network-adapter driver running on the external device; and

processing the transactions issued to the UDPD comprises communicating over the peripheral bus with a UDPD driver running on the external device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2024
From: MARCOVITCH, DANIEL; BAR-ILAN, ELIAV; KOREN, RAN AVRAHAM; LISS, LIRAN; DUER, OREN; SHULER, SHAHAF
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 067316/0936 →
Continuity (2)
Continuation 17979013 · Nov 2, 2022
Related Publication 20240289288A1 · Aug 29, 2024
References Cited (13)
US 10255151B1 · Levin et al. · 2019 [cited by applicant]
US 10261880B1 · Levin et al. · 2019 [cited by applicant]
US 10983920B2 · Thyamagondlu · 2021 [cited by examiner]
US 11409685B1 · Kaplan et al. · 2022 [cited by applicant]
US 11550745B1 · Kelm · 2023 [cited by applicant]
US 11573864B1 · Azmy Hassan et al. · 2023 [cited by applicant]
US 20030236929A1 · Nath · 2003 [cited by examiner]
US 20060259291A1 · Dunham · 2006 [cited by examiner]
US 20080092148A1 · Moertl et al. · 2008 [cited by applicant]
US 20130145035A1 · Pope · 2013 [cited by examiner]
US 20190243781A1 · Thyamagondlu · 2019 [cited by examiner]
Arm Limited, “Microprocessor Cores and Processor Technology—Arm®—Processor IP for the Widest Range of Devices,” Product Information, pp. 1-6, years 1995-2024, as downloaded from https://www.arm.com/products/silicon-ip-c… [cited by applicant]
U.S. Appl. No. 17/987,904 Office Action dated Oct. 31, 2024. [cited by applicant]