Faster multi-cell read operation using reverse read calibrations

1. A memory device comprising:

a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and

control logic coupled with the memory array, the control logic to perform operations comprising:

determining a metadata value characterizing a first read level voltage of a highest threshold voltage distribution of a subset of the plurality of memory cells, wherein the metadata value comprises at least one of a failed byte count or a failed bit count;

adjusting, based on the metadata value, a second read level voltage for a second-highest threshold voltage distribution of the subset of the plurality of memory cells; and

causing, to perform an initial calibrated read of the subset of the plurality of memory cells, the adjusted second read level voltage to be applied to a wordline of the plurality of wordlines to read the second-highest threshold voltage distribution.

2. The memory device of claim 1 , wherein the operations further comprise:

adjusting, based on the metadata value, a third read level voltage for a third-highest threshold voltage distribution of the subset of the plurality of memory cells; and

causing, to perform a second calibrated read of the subset of the plurality of memory cells, the adjusted third read level voltage to be applied to the wordline to read the third-highest threshold voltage distribution.

3. The memory device of claim 2 , wherein the operations further comprise:

adjusting, based on the metadata value, a fourth read level voltage for a fourth-highest threshold voltage distribution of the subset of the plurality of memory cells; and

causing, to perform a third calibrated read of the subset of the plurality of memory cells, the adjusted fourth read level voltage to be applied to the wordline to read the fourth-highest threshold voltage distribution.

4. The memory device of claim 2 , wherein the operations further comprise:

performing a bitline precharge and a single strobe sensing of the wordline using the adjusted second read level voltage to determine a second sensed read voltage value; and

performing a bitline precharge and a single strobe sensing of the wordline using the adjusted third read level voltage to determine a third sensed read voltage value.

5. The memory device of claim 1 , wherein the operations further comprise:

performing a dual-strobe sensing operation associated with the first read level voltage to sense at a target read level voltage and at a low read level voltage that is lower than the target read level voltage for the highest threshold voltage distribution; and

storing, in a primary data cache, the target read level voltage and the low read level voltage.

6. The memory device of claim 5 , wherein the operations further comprise:

determining, based on a charge loss characteristic of the highest threshold voltage distribution, that a charge loss of the subset of the plurality of memory cells does not satisfy a threshold voltage drop criterion; and

storing, in a secondary data cache, the target read level voltage with a second sensed read voltage value for the second-highest threshold voltage distribution.

7. The memory device of claim 1 , wherein adjusting the second read level voltage comprises:

identifying, in a lookup table, an entry mapping the metadata value to a corresponding read voltage offset; and

applying the corresponding read voltage offset to the second read level voltage.

8. The memory device of claim 1 , wherein the subset of the plurality of memory cells is a memory page.

9. A method comprising:

determining a metadata value characterizing a first read level voltage of a highest threshold voltage distribution of a subset of a plurality of memory cells of a memory array, wherein the metadata value comprises at least one of a failed byte count or a failed bit count; and

in response to determining that a charge loss associated with the highest threshold voltage distribution satisfies a threshold voltage drop criterion:

adjusting, based on the metadata value, the first read level voltage;

causing, to perform an initial calibrated read of the subset of the plurality of memory cells, the adjusted first read level voltage to be applied to a wordline of the memory array to read the highest threshold voltage distribution;

adjusting, based on the metadata value, a second read level voltage for a second-highest threshold voltage distribution of the subset of the plurality of memory cells; and

causing, to perform a second calibrated read of the subset of the plurality of memory cells, the adjusted second read level voltage to be applied to the wordline to read the second-highest threshold voltage distribution.

10. The method of claim 9 , further comprising:

adjusting, based on the metadata value, a third read level voltage for a third-highest threshold voltage distribution of the subset of the plurality of memory cells; and

causing, to perform a third calibrated read of the subset of the plurality of memory cells, the adjusted third read level voltage to be applied to the wordline to read the third-highest threshold voltage distribution.

11. The method of claim 10 , further comprising:

adjusting, based on the metadata value, a fourth read level voltage for a fourth-highest threshold voltage distribution of the subset of the plurality of memory cells; and

causing, to perform a fourth calibrated read of the subset of the plurality of memory cells, the adjusted fourth read level voltage to be applied to the wordline to read the fourth-highest threshold voltage distribution.

12. The method of claim 9 , further comprising:

performing a bitline precharge and a single strobe sensing of the wordline using the adjusted first read level voltage to determine a first sensed read voltage value; and

performing a bitline precharge and a single strobe sensing of the wordline using the adjusted second read level voltage to determine a second sensed read voltage value.

13. The method of claim 9 , further comprising:

performing a dual-strobe sensing operation associated with the first read level voltage to sense at a target read level voltage and at a low read level voltage that is lower than the target read level voltage for the highest threshold voltage distribution; and

storing, in a primary data cache, the target read level voltage and the low read level voltage.

14. The method of claim 9 , further comprising:

determining, based on a charge loss characteristic of the highest threshold voltage distribution, that the charge loss of the subset of the plurality of memory cells satisfies the threshold voltage drop criterion; and

storing, in a secondary data cache, a first sensed read voltage value for the highest threshold voltage distribution and a second sensed read voltage value for the second-highest threshold voltage distribution.

15. The method of claim 9 , wherein adjusting the first read level voltage comprises:

identifying, in a lookup table, a first entry mapping the metadata value to a corresponding first read voltage offset; and

applying the corresponding the first read voltage offset to first read level voltage.

16. The method of claim 15 , wherein adjusting the second read level voltage comprises:

identifying, in a lookup table, a second entry mapping the metadata value to a corresponding second read voltage offset; and

applying the corresponding the second read voltage offset to second read level voltage.

17. The method of claim 9 , wherein the subset of the plurality of memory cells is a memory page.

18. A non-transitory computer-readable storage medium comprising instructions that, when executed by a controller managing a memory device, cause the controller to:

determine a metadata value characterizing a first read level voltage of a highest threshold voltage distribution of a subset of a plurality of memory cells of a memory array of the memory device, wherein the metadata value comprises at least one of a failed byte count or a failed bit count;

adjust, based on the metadata value, a second read level voltage for a second-highest threshold voltage distribution of the subset of the plurality of memory cells; and

cause, to perform an initial calibrated read of the subset of the plurality of memory cells, the adjusted second read level voltage to be applied to a wordline of the memory array to read the second-highest threshold voltage distribution.

19. The non-transitory computer-readable storage medium of claim 18 , wherein the instructions are further to cause the controller to:

adjust, based on the metadata value, a third read level voltage for a third-highest threshold voltage distribution of the subset of the plurality of memory cells; and

cause, to perform a second calibrated read of the subset of the plurality of memory cells, the adjusted third read level voltage to be applied to the wordline to read the third-highest threshold voltage distribution.

20. The non-transitory computer-readable storage medium of claim 19 , wherein the instructions are further to cause the controller to:

adjust, based on the metadata value, a fourth read level voltage for a fourth-highest threshold voltage distribution of the subset of the plurality of memory cells; and

cause, to perform a third calibrated read of the subset of the plurality of memory cells, the adjusted fourth read level voltage to be applied to the wordline for reading the fourth-highest threshold voltage distribution.