Memory device supporting in-memory MAC operation between ternary input data and binary weight using charge sharing method and operation method thereof
View Patent ↗A memory device includes a memory cell array connected to a first word line, a pair of second word lines, and a bit line and configured to perform a multiply-accumulate (MAC) operation depending on a ternary input provided from the pair of second word lines and a binary weight preset based on the first word line and the bit line; a peripheral circuit configured to control the memory cell array; and an ADC (analog-to-digital converter) circuit configured to convert a voltage value dependent on the MAC operation into a digital value.
1. A memory device comprising:
a memory cell array connected to a first word line, a pair of second word lines, a first operation control line, a second operation control line, a common bit line, and a bit line, and configured to perform a multiply-accumulate (MAC) operation depending on a ternary input provided from the pair of second word lines and a binary weight preset based on the first word line and the bit line;
a peripheral circuit configured to control the memory cell array; and
an ADC (analog-to-digital converter) circuit configured to convert a voltage value dependent on the MAC operation into a digital value,
wherein each memory cell arranged in the memory cell array comprises:
a static random access memory (SRAM) connected to the first word line and the pair of second word lines;
a pair of first transistors connected between the pair of second word lines and a first node, each first transistor having a gate terminal connected to an output terminal of the SRAM;
a second transistor connected between the first node and a second node, and having a gate terminal connected to the first operation control line; and
a third transistor connected between the second node and the common bit line, and having a gate terminal connected to the second operation control line.
2. The memory device of claim 1 , wherein the ternary input corresponds to one of a first voltage, a second voltage, and an intermediate voltage which is an intermediate value of the first voltage.
3. The memory device of claim 2 , further comprising:
an input driver receiving an input signal and having an output terminal connected to the pair of second word lines, and
wherein the input driver is configured to:
precharge the pair of second word lines with the first voltage and the second voltage, and
apply the ternary input to the pair of second word lines in dependence on the input signal when both the first voltage and the second voltage are converted to the intermediate voltage according to charge sharing between the pair of second word lines.
4. The memory device of claim 3 , wherein the input driver is configured to:
drive the pair of second word lines with the first voltage and the second voltage, respectively when the input signal is a ternary value of ‘1’;
maintain the pair of second word lines at the intermediate voltage when the input signal is a ternary value of ‘0’; and
drive the pair of second word lines with the second voltage and the first voltage, respectively, when the input signal is a ternary value of ‘−1’, and
wherein the ternary input corresponds to a driving voltage of the pair of second word lines.
5. The memory device of claim 1 , wherein the binary weight is set to one of binary values ‘1’ and ‘−1’ according to a voltage applied from the bit line.
6. The memory device of claim 1 , wherein, when an ON signal is received from the first operation control line, the memory cell array charges the second node with charges corresponding to a value obtained by multiplying the ternary input by the binary weight, based on that one of the pair of first transistors is turned on based on the ternary input, and
wherein, when an OFF signal from the first operation control line and an ON signal from the second operation control line are received, the memory cell array performs the MAC operation based on sharing charges charged in the second node to the common bit line.
7. A method of operating a memory device comprising a memory cell array connected to a first word line, a pair of second word lines, a first operation control line, a second operation control line, a common bit line, and a bit line, and configured to perform a multiply-accumulate (MAC) operation depending on a ternary input provided from the pair of second word lines and a binary weight preset based on the first word line and the bit line, the method comprising:
performing a multiply-accumulate (MAC) operation depending on a ternary input provided from a pair of second word lines and a binary weight preset based on a first word line and a bit line; and
converting a voltage value dependent on the MAC operation into a digital value,
wherein each memory cell arranged in the memory cell array comprises:
a static random access memory (SRAM) connected to the first word line and the pair of second word lines;
a pair of first transistors connected between the pair of second word lines and a first node, each first transistor having a gate terminal connected to an output terminal of the SRAM;
a second transistor connected between the first node and a second node, and having a gate terminal connected to the first operation control line; and
a third transistor connected between the second node and the common bit line, and having a gate terminal connected to the second operation control line.
8. The method of claim 7 , further comprising:
precharging the pair of second word lines with a first voltage and a second voltage, wherein the ternary input corresponds to one of the first voltage, the second voltage, and an intermediate voltage which is an intermediate value of the first voltage; and
applying the ternary input to the pair of second word lines based on an input signal when both the first voltage and the second voltage are converted to the intermediate voltage according to charge sharing between the pair of second word lines.