Integrated circuit with coil below and overlapping a pad
An integrated circuit including a chip substrate having an upper isolation layer with a pad thereon and a coil located below the pad, where, in a dimension perpendicular to a surface of the chip substrate, a perimeter of the coil overlaps with a perimeter of the pad.
1. An integrated circuit, comprising:
a chip substrate having a upper isolation layer with a pad thereon; and
a coil located below the metal pad, wherein, in a dimension perpendicular to a surface of the chip substrate, a perimeter of the coil overlaps with a perimeter of the pad, wherein the coil is electrically connected to the pad by one or more conductive interconnects.
2. The integrated circuit of claim 1 , wherein the conductive interconnects pass through one or more intermediate isolation layers located between the upper isolation layer and the lower isolation layer.
3. An integrated circuit, comprising:
a chip substrate having a upper isolation layer with a pad thereon; and
a coil located below the metal pad, wherein, in a dimension perpendicular to a surface of the chip substrate, a perimeter of the coil overlaps with a perimeter of the pad, wherein the coil is connected by one or more conductive interconnects to an electrostatic discharge diode located on a base isolation layer of the chip substrate.
4. The integrated circuit of claim 3 , wherein the conductive interconnects pass through one or more redistribution isolation layers located between the lower isolation layer and the base isolation layer.
5. An integrated circuit, comprising:
a chip substrate having a upper isolation layer with a pad thereon; and
a coil located below the metal pad, wherein, in a dimension perpendicular to a surface of the chip substrate, a perimeter of the coil overlaps with a perimeter of the pad, wherein the coil is connected by one or more conductive interconnects to integrated circuit devices located on a base isolation layer of the chip substrate.
6. An integrated circuit package, comprising:
an integrated circuit, including:
a chip substrate having a upper isolation layer with a pad thereon;
a coil located below the pad, wherein, in a dimension perpendicular to a surface of the chip substrate, a perimeter of the coil overlaps with a perimeter of the pad;
one or more conductive first interconnects electrically connecting the coil to the pad;
one or more conductive second interconnects electrically connecting the coil to an electrostatic discharge diode located on a base isolation layer of the chip substrate; and
one or more conductive third interconnects electrically connecting the coil to integrated circuit devices located on the base isolation layer.
7. The package of claim 6 , further including an input output solder bump connected to the pad.
8. The package of claim 6 , wherein the integrated circuit devices includes one or more of a transistor, resistor, capacitor, varactor or diode.
9. A computer having one or more circuits that include the integrated circuit of claim 6 .
10. An integrated circuit package, comprising:
an integrated circuit, including:
a chip substrate having a upper isolation layer with a pad thereon;
a coil located below the pad, wherein, in a dimension perpendicular to a surface of the chip substrate, an area defined by a perimeter of the coil overlaps with an area defined by a perimeter of the pad such that the area of the pad is within the area of the coil, the area of the coil is within the area of the pad, or, the area of the coil is partially outside the area of the pad;
one or more conductive first interconnects electrically connecting the coil to the pad;
one or more conductive second interconnects electrically connecting the coil to an electrostatic discharge diode located on a base isolation layer of the chip substrate; and
one or more conductive third interconnects electrically connecting the coil to integrated circuit devices located on the base isolation layer.
11. A computer having one or more circuits that include the integrated circuit of claim 10 .