Power semiconductor device and method for fabricating the same
A power semiconductor device includes: a semiconductor layer; a well region positioned inside the semiconductor layer and having a first conductive type; a source region positioned on the well region and having a second conductive type; a gate region making contact with a side surface of the well region to surround the well region; and a drift region making contact with bottom surfaces of the well region and the gate region and having the second conductive type. The drift region may include a protrusion region extending from the drift region and making contact with another side surface of the well region.
1. A power semiconductor device comprising:
a semiconductor layer;
a well region positioned inside the semiconductor layer and having a first conductive type;
a source region positioned on the well region and having a second conductive type;
a gate region making contact with a side surface of the well region to surround the well region; and
a drift region making contact with bottom surfaces of the well region and the gate region and having the second conductive type,
wherein the drift region includes a protrusion region extending from the drift region and making contact with another side surface of the well region, and
wherein the gate region makes contact with the well region on at least three surfaces.
2. The power semiconductor device of claim 1 , further comprising:
a first channel region and a second channel region positioned in contact regions between the gate region and the well region,
wherein the first channel region includes a horizontal channel extending from the source region toward the protrusion region, and
wherein the second channel region includes a vertical channel extending a side surface of the gate region from the source region.
3. The power semiconductor device of claim 1 , wherein a doping concentration of the source region is higher than a doping concentration of the drift region.
4. The power semiconductor device of claim 1 , further comprising:
a contact region positioned on the well region and having the first conductive type,
wherein a doping concentration of the contact region is higher than a doping concentration of the well region.
5. The power semiconductor device of claim 1 , further comprising:
a contact region positioned on the well region and having the first conductive type; and
a source electrode making contact with the source region and the contact region.
6. The power semiconductor device of claim 1 , further comprising:
a substrate region positioned under the drift region and having the second conductive type; and
a drain electrode positioned under the substrate region and making contact with the substrate region,
wherein a doping concentration of the substrate region be higher than a doping concentration of the drift region.
7. The power semiconductor device of claim 1 , wherein the well region has a circular sectional surface.
8. The power semiconductor device of claim 1 , wherein the well region has a polygonal sectional surface having at least three sides.
9. The power semiconductor device of claim 1 , wherein the well region is positioned at a first depth from one surface of the semiconductor layer,
wherein the gate region is positioned at a second depth from the one surface of the semiconductor layer,
wherein the first depth is greater than the second depth, and
wherein the well region includes an extension region extending along a bottom surface of the gate region.
10. A method for fabricating a power semiconductor device, the method comprising:
forming a drift region of a second conductive type on a semiconductor layer;
forming a well region of a first conductive type at a first depth from one surface of the semiconductor layer;
forming a source region of the second conductive type on the well region;
forming a contact region of the first conductive type on the well region; and
forming a gate region by recessing the semiconductor layer and the well region by a second depth to make contact with a side surface of the well region and to surround the well region,
wherein the drift region includes a protrusion region extending from the drift region and making contact with another side surface of the well region, and
wherein the gate region is formed to make contact with the well region on at least three surfaces.
11. The method of claim 10 , wherein the first depth is greater than the second depth.
12. The method of claim 10 , wherein the contact region is doped at a doping concentration higher than a doping concentration of the well region.
13. The method of claim 10 , wherein the source region is doped at a doping concentration higher than a doping concentration of the drift region.
14. The method of claim 10 , further comprising:
forming a first channel region and a second channel region in contact regions between the gate region and the well region,
wherein the first channel region includes a horizontal channel extending from the source region toward the protrusion region, and
wherein the second channel region includes a vertical channel extending along a side surface of the gate region from the source region.
15. The method of claim 10 , further comprising:
forming a source electrode making contact with the source region and the contact region.
16. A power semiconductor device comprising:
a semiconductor layer;
a well region positioned inside the semiconductor layer and having a first conductive type;
a source region positioned on the well region and having a second conductive type;
a gate region making contact with a side surface of the well region to surround the well region; and
a drift region making contact with bottom surfaces of the well region and the gate region and having the second conductive type,
wherein the drift region includes a protrusion region extending from the drift region and making contact with another side surface of the well region, and
wherein the well region has a circular sectional surface or has a polygonal sectional surface having at least three sides.