IP Library › Granted Patent US 12,249,966
Granted Patent B2
US 12,249,966 · App. 18/648,789 · Granted Mar 11, 2025

Multi-mode multi-port driver for transceiver interface

Inventors: Yung-Chung Lo (San Diego, CA); Hyejeong Song (San Diego, CA); Bhushan Shanti Asuri (San Diego, CA); Sahar Nozari (San Diego, CA)
Assignee: QUALCOMM Incorporated
H03F3/245H03F1/0211H04B1/40H03F2200/294H03F2200/451
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Quick Facts
Patent No.
US 12,249,966
App. No.
18/648,789
Granted
Mar 11, 2025
Kind
B2
Abstract

A load line impedance modulation circuit includes a magnetic circuit, an adjustable capacitance coupled to an output of the magnetic circuit, and a plurality of adjustable resistances coupled to the output of the magnetic circuit, wherein the plurality of adjustable resistances are configured to select from available output ports, an impedance presented by the load line impedance modulation circuit being adjustable dependent on at least a number of selected output ports.

Claims (28)

1. A load line impedance modulation circuit, comprising:

a magnetic circuit;

an adjustable capacitance coupled to an output of the magnetic circuit; and

a plurality of adjustable resistances coupled to the output of the magnetic circuit,

wherein the plurality of adjustable resistances are configured to select from available output ports, an impedance presented by the load line impedance modulation circuit being adjustable dependent on at least a number of selected output ports.

2. The load line impedance modulation circuit of claim 1 , wherein an impedance presented by the load line impedance modulation circuit corresponds to a high impedance when configured for one selected output port in a user equipment (UE) in a low power mode.

3. The load line impedance modulation circuit of claim 1 , wherein an impedance presented by the load line impedance modulation circuit corresponds to a low impedance when configured for more than one selected output port in a customer premises equipment (CPE) in a high power mode.

4. The load line impedance modulation circuit of claim 1 , wherein the load line impedance modulation circuit is implemented at an intermediate frequency (IF) in a multiple-band millimeter-wave (mmW) communication system.

5. The load line impedance modulation circuit of claim 1 , wherein the plurality of adjustable resistances comprises a resistive splitter configured to provide power splitting among the output ports.

6. The load line impedance modulation circuit of claim 1 , wherein the plurality of adjustable resistances are configured to select two output ports or four output ports.

7. The load line impedance modulation circuit of claim 1 , wherein each of the plurality of adjustable resistances comprises a first switch in parallel with a resistor and a second switch.

8. The load line impedance modulation circuit of claim 1 , wherein at least one of the available output ports is coupled between a driver amplifier (DA) and a power amplifier.

9. The load line impedance modulation circuit of claim 8 , wherein no amplifier stage is coupled between the driver amplifier (DA) and any of the available output ports.

10. The load line impedance modulation circuit of claim 8 , wherein the driver amplifier (DA) comprises a first DA configured for a first band and coupled to the available output ports through the load line impedance modulation circuit, and wherein a second DA configured for a second band is coupled to the available output ports through a portion of the load line impedance modulation circuit.

11. The load line impedance modulation circuit of claim 8 , wherein the DA is configured to provide a transmit signal to the selected output ports, and wherein the selected output ports are configured to receive a receive signal from components external to a transceiver chip in which the load line impedance modulation circuit is disposed.

12. The load line impedance modulation circuit of claim 1 , wherein the selected output ports are coupled to a respective plurality of millimeter wave integrated circuits forming a phased array system.

13. The load line impedance modulation circuit of claim 1 , wherein the available output ports are coupled to a common node.

14. A method for load line impedance modulation, comprising:

adjusting a capacitance coupled to an output of a magnetic circuit; and

selectively adjusting a plurality of adjustable resistances coupled to the output of the magnetic circuit to select from a plurality of available output ports, the load line impedance being adjustable dependent on at least a number of selected available output ports.

15. The method of claim 14 , further comprising selectively adjusting the load line impedance to a high impedance when configured for one selected available output port in a user equipment (UE) in a low power mode.

16. The method of claim 14 , further comprising selectively adjusting the load line impedance to a low impedance when configured for more than one selected available output port in a customer premises equipment (CPE) in a high power mode.

17. The method of claim 14 , wherein the capacitance is adjusted based on a desired load line impedance.

18. A device for load line impedance modulation, comprising:

means for adjusting a capacitance coupled to an output of a magnetic circuit; and

means for selectively adjusting a plurality of adjustable resistances coupled to the output of the magnetic circuit to select from a plurality of available output ports, the load line impedance being adjustable dependent on at least a number of selected available output ports.

19. The device of claim 18 , further comprising means for selectively adjusting the load line impedance to a high impedance when configured for one selected available output port in a user equipment (UE) in a low power mode.

20. The device of claim 18 , further comprising means for selectively adjusting the load line impedance to a low impedance when configured for more than one selected available output port in a customer premises equipment (CPE) in a high power mode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2024
From: LO, YUNG-CHUNG; SONG, HYEJEONG; ASURI, BHUSHAN SHANTI; NOZARI, SAHAR
To: QUALCOMM INCORPORATED
Reel/Frame 068051/0038 →
Continuity (3)
Division 17478431 · Sep 17, 2021
Provisional Application 63233585 · Aug 16, 2021
Related Publication 20240275343A1 · Aug 15, 2024
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