Semiconductor device with programmable structure and method for fabricating the same
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a buried gate structure positioned in the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the buried gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.
1. A method for fabricating a semiconductor device, comprising:
providing a substrate;
forming an isolation layer in the substrate to define an active area of the substrate, wherein the active area comprises a transistor portion and a programmable portion extending from the transistor portion;
forming a buried gate structure in the transistor portion;
forming a drain region in the programmable portion and the transistor portion, and adjacent to the gate structure;
forming a source region in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the buried gate structure interposed therebetween;
forming a middle insulating layer on the programmable portion; and
forming an upper conductive layer on the middle insulating layer;
wherein the drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.
2. The method of claim 1 , wherein the buried gate structure comprises:
a buried gate insulating layer inwardly formed in the transistor portion and having a U-shaped cross-sectional profile;
a buried gate conductive layer on the buried gate insulating layer; and
a buried gate capping layer on the buried gate insulating layer and the buried gate conductive layer.
3. The method of claim 1 , wherein a length of the source region is less than a length of the drain region in a top-view perspective.
4. The method of claim 3 , wherein the programmable portion is extending along a first direction and the programmable structure is extending along a second direction perpendicular to the first direction.
5. The method of claim 1 , wherein a width of the programmable portion is less than a width of the transistor portion.
6. The method of claim 1 , wherein the buried gate structure comprises:
a buried gate insulating layer inwardly positioned in the transistor portion and having a U-shaped cross-sectional profile;
a buried gate conductive layer positioned on the buried gate insulating layer; and
a buried gate capping layer positioned on the buried gate insulating layer and the buried gate conductive layer.
7. The method of claim 1 , further comprising forming two spacers on sidewalls of the middle insulating layer and the upper conductive layer.