IP Library › Granted Patent US 12,254,186
Granted Patent B2
US 12,254,186 · App. 17/988,329 · Granted Mar 18, 2025

I/o expanders for supporting peak power management

Inventor: Liang Yu (Boise, ID)
Assignee: Micron Technology, Inc.
G06F3/0613G06F3/0659G06F3/0679
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Quick Facts
Patent No.
US 12,254,186
App. No.
17/988,329
Granted
Mar 18, 2025
Kind
B2
Abstract

A memory device includes sets of memory dies. Each set of memory dies includes a memory dies associated with a respective channel of a plurality of channels, and each channel of the plurality of channels has a respective ready busy (RB) signal. The memory device further includes an input/output (I/O) expander to perform operations including receiving at least one command to perform clock synchronization associated with a clock signal with respect to the plurality of sets of memory dies, and in response to receiving the command, causing circuitry of the I/O expander to be configured to create an RB signal short with respect to a particular combination of channels. The clock synchronization is associated with peak power management (PPM) initialization.

Claims (29)

1. A memory device comprising:

a plurality of sets of memory dies, wherein each set of memory dies comprises a plurality of memory dies associated with a respective channel of a plurality of channels, each channel of the plurality of channels having a respective ready busy (RB) signal; and

an input/output (I/O) expander coupled to the plurality of sets of memory dies by the plurality of channels, the I/O expander to perform operations comprising:

receiving at least one command to perform peak power management (PPM) clock synchronization associated with a clock signal with respect to the plurality of sets of memory dies, wherein the PPM clock synchronization is associated with PPM initialization; and

in response to receiving the at least one command to perform the PPM clock synchronization, causing circuitry of the I/O expander to be configured to trigger the PPM clock synchronization by creating one or more targeted RB signal shorts with respect to a particular combination of channels of the plurality of channels.

2. The memory device of claim 1 , wherein the circuitry comprises a plurality of switches, and wherein causing the circuitry of the I/O expander to be configured to trigger the PPM clock synchronization by creating the RB signal short comprises controlling a state with respect to each switch of the plurality of switches to create the one or more targeted RB signal shorts.

3. The memory device of claim 1 , wherein the at least one command comprises a set feature command.

4. The memory device of claim 1 , wherein the one or more targeted RB signal shorts correspond to at least one of all channels of the plurality of channels, or a pair of channels of the plurality of channels.

5. The memory device of claim 1 , wherein the plurality of channels comprises 4 channels, and the plurality of memory dies comprises 4 memory dies.

6. The memory device of claim 1 , wherein the plurality of memory dies comprises a primary die and a secondary die, and wherein the primary die is to generate the clock signal.

7. The memory device of claim 1 , wherein the I/O expander further comprises at least one of: a multiplexer or AND logic.

8. An input/output (I/O) expander comprising:

circuitry to perform operations comprising:

receiving at least one command to perform peak power management (PPM) clock synchronization associated with a clock signal with respect to a plurality of sets of memory dies, wherein the PPM clock synchronization is associated with PPM initialization, and wherein each set of memory dies comprises a plurality of memory dies associated with a respective channel of a plurality of channels, each channel of the plurality of channels having a respective ready busy (RB) signal; and

in response to receiving the at least one command to perform the PPM synchronization, causing the circuitry to be configured to trigger the PPM clock synchronization by creating one or more targeted RB signal shorts with respect to a particular combination of channels of the plurality of channels.

9. The I/O expander of claim 8 , wherein the circuitry comprises a plurality of switches, and wherein causing the circuitry of the I/O expander to be configured to trigger the PPM clock synchronization by creating the RB signal short comprises controlling a state with respect to each switch of the plurality of switches to create the one or more targeted RB signal shorts.

10. The I/O expander of claim 8 , wherein the at least one command comprises a set feature command.

11. The I/O expander of claim 8 , wherein the one or more targeted RB signal shorts correspond to at least one of all channels of the plurality of channels, or a pair of channels of the plurality of channels.

12. The I/O expander of claim 8 , wherein the plurality of channels comprises 4 channels, and the plurality of memory dies comprises 4 memory dies.

13. The I/O expander of claim 8 , wherein the plurality of memory dies comprises a primary die and a secondary die, and wherein the primary die is to generate the clock signal.

14. The I/O expander of claim 8 , further comprising at least one of: a multiplexer or AND logic.

15. A method comprising:

receiving, by an I/O expander, at least one command to perform peak power management (PPM) clock synchronization associated with a clock signal with respect to a plurality of sets of memory dies, wherein the PPM clock synchronization is associated with PPM initialization, and wherein each set of memory dies comprises a plurality of memory dies associated with a respective channel of a plurality of channels, each channel of the plurality of channels having a respective ready busy (RB) signal; and

in response to receiving the at least one command to perform the PPM clock synchronization, causing, by the I/O expander, the PPM clock synchronization to be triggered by creating one or more targeted RB signal shorts with respect to a particular combination of channels of the plurality of channels.

16. The method of claim 15 , wherein causing the PPM clock synchronization to be triggered comprises controlling a state with respect to each switch of a plurality of switches to create the one or more targeted RB signal shorts.

17. The method of claim 15 , wherein the at least one command comprises a set feature command.

18. The method of claim 15 , wherein the one or more targeted RB signal shorts correspond to at least one of all channels of the plurality of channels, or a pair of channels of the plurality of channels.

19. The method of claim 15 , wherein the plurality of channels comprises 4 channels, and the plurality of memory dies comprises 4 memory dies.

20. The method of claim 15 , wherein the plurality of memory dies comprises a primary die and a secondary die, and wherein the primary die is to generate the clock signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2022
From: YU, LIANG
To: MICRON TECHNOLOGY, INC.
Reel/Frame 061795/0813 →
Continuity (2)
Provisional Application 63292059 · Dec 21, 2021
Related Publication 20230195317A1 · Jun 22, 2023
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