Memory initialization apparatus and method, and computer system
A memory initialization apparatus and method, and a computer system are provided. The memory initialization apparatus includes a first processor core and a memory controller that includes at least one second processor core. In a memory initialization process, the first processor core may invoke the second processor core to perform memory initialization. This helps to shorten memory initialization duration.
1. A memory initialization apparatus, comprising:
a memory controller comprising at least one second processor core; and
a first processor core configured to invoke the at least one second processor core of the memory controller to perform memory initialization,
wherein the first processor core is further configured to:
after channel initialization is completed for any memory channel, initialize, by using the any memory channel and at least one memory chip connected to the any memory channel, a component other than the memory chip.
2. The memory initialization apparatus according to claim 1 , wherein the memory controller further comprises at least one memory channel, and each memory channel is configured to connect to at least one memory chip; and
the first processor core is configured to:
invoke the at least one second processor core to perform channel initialization on the at least one memory channel.
3. The memory initialization apparatus according to claim 2 , wherein the channel initialization comprises at least one of memory training or memory testing.
4. The memory initialization apparatus according to claim 2 , wherein the first processor core is further configured to:
after channel initialization is completed for each of the at least one memory channel, perform system configuration on the memory controller and a memory chip connected to the at least one memory channel, to generate management information, wherein the management information is used by the first processor core to manage the memory chip connected to the at least one memory channel.
5. The memory initialization apparatus according to claim 2 , wherein the at least one second processor core is connected to the at least one memory channel respectively; and
the first processor core is configured to:
after initialization configuration is completed for a first memory channel and at least one first memory chip connected to the first memory channel, invoke a second processor core connected to the first memory channel, wherein the first memory channel is any one of the at least one memory channel.
6. The memory initialization apparatus according to claim 5 , wherein the first processor core is configured to:
after invoking the second processor core correspondingly connected to the first memory channel, continue to perform initialization configuration on a second memory channel and at least one second memory chip connected to the second memory channel, wherein the second memory channel is any memory channel for which channel initialization is not started in the at least one memory channel.
7. The memory initialization apparatus according to claim 5 , wherein the first processor core is further configured to:
after the memory initialization is completed, invoke the second processor core connected to the first memory channel, to manage output power of a power supply that is configured to supply power to the at least one first memory chip.
8. The memory initialization apparatus according to claim 7 , wherein the second processor core connected to the first memory channel is further configured to:
monitor a working status of the at least one first memory chip; and
adjust the output power of the power supply based on the working status of the at least one first memory chip.
9. The memory initialization apparatus according to claim 1 , wherein the memory controller further comprises at least one storage circuit connected to the at least one second processor core respectively;
the first processor core is configured to separately write invocation information to the at least one storage circuit, wherein the invocation information is information used to perform the memory initialization; and
the at least one second processor core is configured to read the invocation information from a correspondingly connected storage circuit and execute the invocation information.
10. The memory initialization apparatus according to claim 9 , wherein the invocation information comprises at least one instruction; and
the first processor core is configured to:
invoke, by using an instruction sequence number, the at least one second processor core to execute an instruction corresponding to the instruction sequence number.
11. The memory initialization apparatus according to claim 9 , wherein firmware of the at least one second processor core is stored in a nonvolatile memory and can be updated, and the firmware comprises the invocation information.
12. The memory initialization apparatus according to claim 1 , wherein the first processor core is further configured to:
after the memory initialization is completed, invoke the at least one second processor core to perform memory training.
13. The memory initialization apparatus according to claim 1 , wherein the first processor core is further configured to:
after the memory initialization is completed, invoke the at least one second processor core to perform troubleshooting.
14. The memory initialization apparatus according to claim 13 , wherein the at least one second processor core is further configured to:
when the memory controller is faulty, determine a faulty node in the memory controller, and feed back location information of the faulty node to the first processor core.
15. A memory initialization method, comprising:
invoking, by a first processor core of an apparatus, at least one second processor core;
performing memory initialization via the invoked at least one second processor core, wherein the apparatus further comprises a memory controller, the memory controller including the at least one second processor core; and
after channel initialization is completed for any memory channel, initializing, by the first processor core by using the any memory channel and at least one memory chip connected to the any memory channel, a component other than the memory chip.
16. The memory initialization method according to claim 15 , wherein the memory controller further comprises at least one memory channel, and each memory channel is configured to connect to at least one memory chip; and
wherein invoking the at least one second processor core comprises:
invoking, by the first processor core, the at least one second processor core to perform channel initialization on the at least one memory channel.
17. The memory initialization method according to claim 16 , wherein the channel initialization comprises at least one of memory training or memory testing.
18. The memory initialization method according to claim 16 , further comprising:
after channel initialization is completed for each of the at least one memory channel, performing, by the first processor core, system configuration on the memory controller and a memory chip connected to the at least one memory channel, to generate management information, wherein the management information is used by the first processor core to manage the memory chip connected to the at least one memory channel.
19. The memory initialization method according to claim 16 , wherein the at least one second processor core is connected to the at least one memory channel respectively; and
wherein invoking the at least one second processor core to perform channel initialization on the at least one memory channel comprises:
after initialization configuration is completed for a first memory channel and at least one first memory chip connected to the first memory channel, invoking, by the first processor core, a second processor core connected to the first memory channel, wherein the first memory channel is any one of the at least one memory channel.
20. The memory initialization method according to claim 19 , wherein invoking the at least one second processor core to perform channel initialization on the at least one memory channel comprises:
after invoking the second processor core correspondingly connected to the first memory channel, continuing, by the first processor core, to perform initialization configuration on a second memory channel and at least one second memory chip connected to the second memory channel, wherein the second memory channel is any memory channel for which channel initialization is not started in the at least one memory channel.
21. The memory initialization method according to claim 19 , wherein after the memory initialization is completed, the method further comprises:
invoking, by the first processor core, the second processor core connected to the first memory channel, to manage output power of a power supply that is configured to supply power to the at least one first memory chip.
22. The memory initialization method according to claim 21 , further comprising:
monitoring, by the second processor core connected to the first memory channel, a working status of the at least one first memory chip; and
adjusting, by the second processor core connected to the first memory channel, the output power of the power supply based on the working status of the at least one first memory chip.
23. The memory initialization method according to claim 15 , wherein the memory controller further comprises at least one storage circuit connected to the at least one second processor core respectively; and
wherein invoking the at least one second processor core comprises:
separately writing, by the first processor core, invocation information into the at least one storage circuit, wherein the invocation information is used to perform the memory initialization; and
reading, by any one of the at least one second processor core, the invocation information from a correspondingly connected storage circuit, and executing the invocation information.
24. The memory initialization method according to claim 23 , wherein the invocation information comprises at least one instruction; and
wherein reading the invocation information from a correspondingly connected storage circuit comprises:
invoking, by the first processor core by using an instruction sequence number, the at least one second processor core to execute an instruction corresponding to the instruction sequence number.
25. The memory initialization method according to claim 23 , wherein firmware of the at least one second processor core is stored in a nonvolatile memory and can be updated, and the firmware comprises the invocation information.
26. The memory initialization method according to claim 15 , wherein after the memory initialization is completed, the method further comprises:
invoking, by the first processor core, the at least one second processor core to perform memory training.
27. The memory initialization method according to claim 15 , wherein after the memory initialization is completed, the method further comprises:
invoking, by the first processor core, the at least one second processor core to perform troubleshooting.
28. A computer system, comprising:
a memory initialization apparatus, comprising:
a memory controller comprising at least one second processor core; and
a first processor core configured to invoke the at least one second processor core of the memory controller to perform memory initialization; and
a memory chip coupled to the memory initialization apparatus,
wherein the first processor core is further configured to:
after a channel initialization is completed for any memory channel connected to the memory chip, initialize, by using the any memory channel and the memory chip, a component other than the memory chip.