Semiconductor structure, method of reading data from semiconductor structure, and method of writing data into semiconductor structure
The present disclosure provides a semiconductor structure, a method of reading data from the semiconductor structure, and a method of writing data into the semiconductor structure. The semiconductor structure includes: a memory matrix, including a plurality of magnetic storage domains arranged in a staggered manner and including a first end, a second end, and an intermediate portion; and a reading and writing circuit, connected to the intermediate portion of the memory matrix and configured to write data into the magnetic storage domains and read data from the magnetic storage domains.
1. A semiconductor structure, comprising:
a memory matrix, comprising a plurality of magnetic storage domains arranged in a staggered manner and comprising a first end, a second end, and an intermediate portion relative positions of the plurality of magnet storage domains in the memory matrix being able to move within the memory matrix under action of a drive current; and
a reading and writing circuit, connected to the intermediate portion of the memory matrix and configured to write data into the magnetic storage domains and read data from the magnetic storage domains.
2. The semiconductor structure according to claim 1 , wherein the reading and writing circuit comprises an isolation layer, a magnetic tunnel junction, and a first control circuit.
3. The semiconductor structure according to claim 2 , wherein the magnetic tunnel junction comprises a first electrode, a free layer, a tunneling barrier layer, a reference layer, and a second electrode arranged in a stacked manner, the first electrode being connected to the isolation layer.
4. A semiconductor structure, comprising:
a memory matrix, comprising a plurality of magnetic storage domains arranged in a staggered manner and comprising a first end, a second end, and an intermediate portion,
a reading and writing circuit, connected to the intermediate portion of the memory matrix and configured to write data into the magnetic storage domains and read data from the magnetic storage domains, wherein the reading and writing circuit comprises an isolation layer, a magnetic tunnel junction, and a first control circuit, and the magnetic tunnel junction comprises a first electrode, a free layer, a tunneling barrier layer, a reference layer, and a second electrode arranged in a stacked manner, the first electrode being connected to the isolation layer;
a first source line, connected to the reading and writing circuit;
a first bit line, connected to the reading and writing circuit; and
a drive device, comprising a second source line provided at the first end of the memory matrix and a second bit line provided at the second end of the memory matrix.
5. The semiconductor structure according to claim 4 , wherein
the first source line is connected to the second electrode of the reading and writing circuit; and the first bit line is connected to the first electrode of the reading and writing circuit.
6. The semiconductor structure according to claim 4 , wherein
a second control circuit is further provided between the first end of the memory matrix and the second source line.
7. The semiconductor structure according to claim 6 , wherein the second control circuit comprises a transistor.
8. The semiconductor structure according to claim 7 , wherein the first control circuit comprises a transistor.
9. The semiconductor structure according to claim 8 , wherein at least one of the first control circuit or the second control circuit comprises a transistor; and the semiconductor structure further comprises a word line connected to a gate of the transistor of the at least one of the first control circuit or the second control circuit.
10. The semiconductor structure according to claim 4 , wherein the isolation layer is connected to the memory matrix, and the isolation layer is connected to at least three of the magnetic storage domains.
11. The semiconductor structure according to claim 1 , wherein the first end comprises a plurality of consecutive magnetic storage domains of a first direction, and the second end comprises a plurality of consecutive magnetic storage domains of a second direction, the first direction being different from the second direction.
12. The semiconductor structure according to claim 1 , wherein adjacent ones of the magnetic storage domains are arranged in a staggered manner.
13. The semiconductor structure according to claim 1 , wherein an overlapping region is provided between adjacent ones of the magnetic storage domains, and a maximum size of the overlapping region is 35% to 70% of a width of the magnetic storage domain.
14. A method of reading data from the semiconductor structure according to claim 4 , comprising:
inputting a second read signal into a second source line and a second bit line in response to a data read command, to drive a magnetic storage domain at a target position to move to a position corresponding to a reading and writing circuit; and
inputting a first read signal into a first source line and a first bit line, to read the data from the magnetic storage domain at the position corresponding to the reading and writing circuit.
15. A method of writing data into the semiconductor structure according to claim 4 , comprising:
inputting a second write signal into a second source line and a second bit line in response to a data write command, to drive a magnetic storage domain at a target position to move to a position corresponding to a reading and writing circuit; and
inputting a first write signal into a first source line and a first bit line, to write the data into the magnetic storage domain at the position corresponding to the reading and writing circuit.
16. The semiconductor structure according to claim 3 , further comprising:
a first source line, connected to the reading and writing circuit;
a first bit line, connected to the reading and writing circuit; and
a drive device, comprising a second source line provided at the first end of the memory matrix and a second bit line provided at the second end of the memory matrix.
17. The semiconductor structure according to claim 16 , wherein
a second control circuit is further provided between the first end of the memory matrix and the second source line.
18. The semiconductor structure according to claim 17 , wherein at least one of the first control circuit or the second control circuit comprises a transistor; and the semiconductor structure further comprises a word line connected to a gate of the transistor of the at least one of the first control circuit or the second control circuit.
19. The semiconductor structure according to claim 16 , wherein the isolation layer is connected to the memory matrix, and the isolation layer is connected to at least three of the magnetic storage domains.
20. The semiconductor structure according to claim 4 , wherein an overlapping region is provided between adjacent ones of the magnetic storage domains, and a maximum size of the overlapping region is 35% to 70% of a width of the magnetic storage domain.