Granted Patent B2

US 12,255,065 · App. 18/529,024 · Granted Mar 18, 2025

Inventors: Hyun-Suk Lee (Suwon-si, KR); Jungoo Kang (Seoul, KR); Gihee Cho (Yongin-si, KR); Sanghyuck Ahn (Daegu, KR)

Assignee: Samsung Electronics Co., Ltd.

H01L21/0228H01L21/12H01L21/302H01L21/76885

Abstract

Claims (47)

1. A method of manufacturing a semiconductor device, the method comprising:

forming electrode holes by etching a mold structure including a mold layer and a support layer which are stacked on a substrate;

forming lower electrode pillars filling the electrode holes;

etching a portion of the support layer between the lower electrode pillars to form a support pattern having a through-hole exposing a portion of a top surface of the mold layer;

forming metal residual patterns on a surface of the support pattern;

removing the mold layer through the through-hole to expose sidewalls of the lower electrode pillars; and

selectively forming lower electrode patterns on the sidewalls and top surfaces of the lower electrode pillars,

wherein the metal residual patterns are spaced apart from the lower electrode patterns.

2. The method of claim 1 , wherein the forming of the lower electrode patterns comprises:

providing a niobium precursor, and

wherein the niobium precursor includes fluorine.

3. The method of claim 1 ,

wherein the metal residual patterns have hemispherical shapes when viewed in a cross-sectional view, and

wherein the metal residual patterns are formed together with the lower electrode patterns in the forming of the lower electrode patterns.

4. The method of claim 1 , wherein the lower electrode patterns are formed to expose a surface of the support pattern.

5. The method of claim 1 , wherein the mold layer includes a silicon nitride layer, and wherein the support layer includes a silicon oxide layer.

6. A method of manufacturing a semiconductor device, the method comprising:

forming electrode holes by etching a mold structure including a mold layer and a support layer which are stacked on a substrate;

forming lower electrode pillars filling the electrode holes;

etching a portion of the support layer between the lower electrode pillars to form a support pattern having a through-hole exposing the mold layer;

removing the mold layer through the through-hole to expose sidewalls of the lower electrode pillars; and

forming lower electrode patterns on the sidewalls and top surfaces of the lower electrode pillars,

wherein the forming of the lower electrode patterns comprises supplying a niobium precursor,

wherein the niobium precursor includes a fluorine.

7. The method of claim 6 , wherein the forming of the lower electrode patterns further comprises supplying a source gas to adsorb the source gas on the sidewalls and the top surfaces of the lower electrode pillars.

8. The method of claim 7 , wherein the source gas includes NH 3 , N 2 , O 2 or O 3 .

9. The method of claim 7 , wherein the forming of the lower electrode patterns comprises combining the niobium precursor and the source gas on the sidewalls and top surfaces of the lower electrode pillars.

10. The method of claim 9 , wherein a formation rate of a layer by a combination of the niobium precursor and the source gas on the sidewalls and top surfaces of the lower electrode pillars is greater than a formation rate of a layer by a combination of the niobium precursor and the source gas on surfaces of the support pattern.

11. The method of claim 6 , wherein the support layer includes a material having an etch selectivity with respect to the mold layer.

12. The method of claim 6 , further comprising forming metal residual patterns on a surface of the support pattern,

wherein the metal residual patterns are formed together with the lower electrode patterns.

13. The method of claim 12 , wherein the metal residual patterns and the lower electrode patterns include a niobium.

14. A method of manufacturing a semiconductor device, the method comprising:

forming an electrode hole by etching a mold structure including a mold layer and a support layer which are stacked on a substrate;

forming a lower electrode pillar filling the electrode hole, a sidewall of the lower electrode pillar comprising a first portion in contact with the molding layer and a second portion in contact with the support layer;

etching the support layer to form a support pattern;

removing the mold layer to expose the first portion of the sidewall of the lower electrode pillar; and

forming a lower electrode pattern on the lower electrode pillar,

wherein a top surface of the support pattern comprises a first portion connected to the sidewall of the lower electrode pillar and a second portion spaced apart from the sidewall of the lower electrode pillar,

wherein the lower electrode pattern is in contact with the first portion of the sidewall of the lower electrode pillar and the first portion of the top surface of the support pattern, and is spaced apart from the second portion of the top surface of the support pattern,

wherein the lower electrode pillar and the lower electrode pattern comprise different respective materials.

15. The method of claim 14 , wherein the lower electrode pattern is spaced apart from the second portion of the sidewall of the lower electrode pillar.

16. The method of claim 14 , wherein a sidewall of the support pattern is spaced apart from the lower electrode pattern.

17. The method of claim 14 , further comprising forming a dielectric layer,

wherein the dielectric layer is spaced apart from the sidewall of the lower electrode pillar.

18. The method of claim 17 , wherein the dielectric layer and the lower electrode pattern have a tetragonal structure.

19. The method of claim 14 , further comprising oxidizing the lower electrode pattern to form a metal oxide pattern.

Priority Claims (1)

Continuity (3)

References Cited (25)