Liner layer for backside contacts of semiconductor devices
The present disclosure describes a semiconductor device that includes a transistor. The transistor includes a source/drain region that includes a front surface and a back surface opposite to the front surface. The transistor includes a salicide region on the back surface and a channel region in contact with the source/drain region. The channel region has a front surface co-planar with the front surface of the source/drain region. The transistor further includes a gate structure disposed on a front surface of the channel region. The semiconductor device also includes a backside contact structure that includes a conductive contact in contact with the salicide region and a liner layer surrounding the conductive contact.
1. A semiconductor device, comprising:
a transistor, comprising:
a source/drain region, comprising:
a front surface and a back surface opposite to the front surface; and a salicide region on the back surface;
a channel region in contact with the source/drain region and comprising a front surface co-planar with the front surface of the source/drain region; and
a gate structure disposed on the front surface of the channel region; and
a backside contact structure, comprising:
a conductive contact in contact with the salicide region; and
a liner layer surrounding the conductive contact, wherein a horizontal interface between the liner layer and the source/drain region is coplanar with a horizontal interface between the salicide region and the conductive contact.
2. The semiconductor device of claim 1 , wherein the channel region comprises a stack of nanowires in contact with the source/drain region.
3. The semiconductor device of claim 2 , further comprising:
a gate dielectric layer wrapped around a nanowire of the stack of nanowires; and
a spacer in contact with the nanowire and the gate dielectric layer.
4. The semiconductor device of claim 3 , wherein the liner layer is in contact with the spacer.
5. The semiconductor device of claim 3 , further comprising a backside dielectric layer in contact with the gate dielectric layer and the liner layer.
6. The semiconductor device of claim 5 , wherein the liner layer is in contact with the source/drain region.
7. The semiconductor device of claim 1 , wherein the liner layer comprises silicon nitride material having an atomic content ratio of nitrogen over silicon between about 1.30 and about 1.33.
8. The semiconductor device of claim 1 , wherein the liner layer comprises silicon carbon nitride having a silicon atomic content between about 10% and about 30%, a carbon atomic content between 30% and about 50%, and a nitrogen atomic content between about 5% and about 10%.
9. The semiconductor device of claim 1 , wherein the liner layer comprises silicon carbon oxide having a silicon atomic content between about 10% and about 30%, a carbon atomic content between 30% and about 50%, and an oxygen atomic content between about 5% and about 10%.
10. The semiconductor device of claim 1 , wherein the liner layer comprises aluminum oxide, hafnium oxide, or silicon boron carbon nitride.
11. A semiconductor device, comprising:
a gate-all-around field effect transistor (GAA FET), comprising:
a plurality of nanowires, wherein a nanowire of the plurality of nanowires comprises a front surface;
a gate dielectric layer wrapping around each nanowire of the plurality of nanowires,
wherein the gate dielectric layer is in contact with the front surface of the nanowire;
a gate electrode disposed on the gate dielectric layer and over the front surface of the nanowire; and
a source/drain (S/D) region in contact with the plurality of nanowires and comprising a front surface and a back surface, wherein the front surface of the S/D region is opposite to the back surface and co-planar with the front surface of the nanowire;
a backside interlayer dielectric (ILD) layer;
a backside contact in the backside ILD layer and comprising:
a salicide layer in contact with a first portion of the back surface of the S/D region;
a conductive contact in contact with the salicide layer; and
a liner layer between the conductive contact and the ILD layer, wherein the liner layer is in contact with a second portion of the back surface of the S/D region, wherein a bottom surface of the liner layer is coplanar with a top surface of the salicide layer; and
an S/D contact in contact with the front surface of the S/D region.
12. The semiconductor device of claim 11 , further comprising a spacer in contact with the nanowire, the liner layer, and the gate dielectric layer.
13. The semiconductor device of claim 11 , wherein the liner layer surrounds the conductive contact.
14. The semiconductor device of claim 11 , further comprising a plurality of spacers, wherein a spacer of the plurality of spacers is in contact with the liner layer and the nanowire of the plurality of nanowires.
15. The semiconductor device of claim 14 , wherein the spacer is in contact with the gate dielectric layer.
16. A semiconductor device, comprising:
a channel region on a substrate;
a gate structure surrounding the channel region;
a source/drain (S/D) region on the substrate and abutting the channel region;
a salicide region having a horizontal bottom surface coplanar with a bottom surface of the gate structure;
a conductive contact on the horizontal bottom surface of the salicide region; and
a liner layer on a side surface of the conductive contact.
17. The semiconductor device of claim 16 , further comprising a spacer between the gate structure and the S/D region.
18. The semiconductor device of claim 16 , further comprising a spacer between the liner layer and the channel region.
19. The semiconductor device of claim 16 , wherein the liner layer is in contact with the S/D region.
20. The semiconductor device of claim 16 , wherein an interface between the salicide region and the S/D region is curved.