Inner spacer structures for gate-all-around field effect transistors
The present disclosure is directed to method for the fabrication of spacer structures between source/drain epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form spacer cavities, and depositing a spacer layer on the fin structure to fill the spacer cavities. Further, treating the spacer layer with a microwave-generated plasma to form an oxygen concentration gradient within the spacer layer outside the spacer cavities and removing, with an etching process, the treated portion of the spacer layer. During the etching process, a removal rate of the etching process for the treated portion of the spacer layer is based on an oxygen concentration within the oxygen concentration gradient.
1. A structure, comprising:
a plurality of nanostructure layers on a substrate;
a source/drain (S/D) structure on the substrate and adjacent to the plurality of nanostructure layers;
a gate structure surrounding the plurality of nanostructure layers; and
a spacer structure interposed between the gate structure and the S/D structure, wherein the spacer structure comprises:
a seam in the spacer structure and separated from a concave side surface of the spacer structure, wherein the concave side surface is between the seam and the S/D structure.
2. The structure of claim 1 , wherein a width of the seam is between about 0.3 nm and about 1 nm.
3. The structure of claim 1 , wherein a length of the seam is between about 3 nm and about 10 nm.
4. The structure of claim 1 , wherein a horizontal distance between a midpoint of the concave side surface and an edge point of the concave side surface is between about 0.6 nm and about 1 nm.
5. The structure of claim 1 , wherein the spacer structure further comprises carbon.
6. The structure of claim 1 , wherein the spacer structure further comprises a flat surface connected to the concave surface and in contact with the plurality of nanostructure layers.
7. The structure of claim 6 , wherein the spacer structure further comprises a convex surface connected to the flat surface and in contact with the gate structure.
8. A structure, comprising:
a plurality of nanostructure layers on a substrate;
a source/drain (S/D) structure on the substrate and adjacent to the plurality of nanostructure layers;
a gate structure surrounding the plurality of nanostructure layers; and
a spacer structure interposed between the plurality of nanostructure layers, wherein the spacer structure comprises:
a concave side surface in contact with the S/D structure;
a convex side surface in contact with the gate structure; and
a flat surface connected to the concave side surface and the convex side surface.
9. The structure of claim 8 , wherein the flat surface is in contact with a bottom surface of one of the plurality of nanostructure layers.
10. The structure of claim 8 , wherein the flat surface is in contact with a top surface of one of the plurality of nanostructure layers.
11. The structure of claim 8 , wherein the flat surface is substantially parallel to a bottom surface of the gate structure.
12. The structure of claim 8 , wherein the convex side surface is in contact with a concave surface of a dielectric layer of the gate structure.
13. The structure of claim 8 , wherein the concave side surface is in contact with a convex surface of the S/D structure.
14. A structure, comprising:
a first nanostructure layer on a substrate;
a gate structure on the first nanostructure layer;
a second nanostructure layer on the gate structure;
a source/drain (S/D) structure adjacent to the first and second nanostructure layers; and
a spacer structure between the S/D structure and the gate structure, wherein the spacer structure comprises a seam with a curved inner surface.
15. The structure of claim 14 , wherein the spacer structure comprises a dielectric material with a dielectric constant less than about 3.9.
16. The structure of claim 14 , wherein the spacer structure comprises a porous material.
17. The structure of claim 14 , wherein the seam is enclosed inside the spacer structure.
18. The structure of claim 14 , wherein the spacer structure further comprises:
a first flat surface in contact with the first nanostructure layer; and
a second flat surface in contact with the second nanostructure layer.
19. The structure of claim 14 , wherein the spacer structure further comprises a convex side surface in contact with a concave surface of the gate structure.
20. The structure of claim 14 , wherein:
the spacer structure further comprises a concave side surface in contact with the S/D structure; and
a horizontal distance between a midpoint of the concave side surface and an edge point of the concave side surface is between about 0.6 nm and about 1 nm.