Semiconductor integrated circuit, receiver device, and reception method
According to one embodiment, a semiconductor integrated circuit includes a first converter, a second converter, and an adjustment circuit. The first converter is configured to sample an analog signal and convert the sampled analog signal to a first digital value based on a first clock signal. The second converter is configured to sample the analog signal and convert the sampled analog signal to a second digital value based on a second clock signal shifted a first phase from the first clock signal. The adjustment circuit is configured to adjust at least one of a gain of each of the first digital value and the second digital value and a phase of each of the first clock signal and the second clock signal based on the first digital value and the second digital value.
1. A semiconductor integrated circuit comprising:
a first converter configured to sample an analog signal and convert the sampled analog signal to a first digital value based on a first clock signal;
a second converter configured to sample the analog signal and convert the sampled analog signal to a second digital value based on a second clock signal shifted a first phase from the first clock signal; and
an adjustment circuit configured to adjust at least one of a gain of each of the first digital value and the second digital value and a phase of each of the first clock signal and the second clock signal based on the first digital value and the second digital value, wherein
the adjustment circuit includes:
a first circuit configured to update a first code based on the first digital value and the second digital value, and update a second code based on the first code; and
a second circuit configured to calibrate a gain of the first digital value based on the first code, and calibrate a gain of the second digital value based on the second code,
or
a third circuit configured to update a third code based on the first digital value and the second digital value, and update a fourth code based on the third code; and
a fourth circuit configured to calibrate a phase of the first clock signal based on the third code, and calibrate a phase of the second clock signal based on the fourth code.
2. The semiconductor integrated circuit according to claim 1 , further comprising
a third converter configured to sample the analog signal and convert the sampled analog signal to a third digital value based on a third clock signal shifted a second phase from the first clock signal,
wherein the adjustment circuit is configured to adjust at least one of a gain of each of the first digital value, the second digital value, and the third digital value and a phase of each of the first clock signal, the second clock signal, and the third clock signal based on the first digital value, the second digital value, and the third digital value.
3. The semiconductor integrated circuit according to claim 2 , wherein
the first circuit is configured to update the first code and a fifth code based on the first digital value, the second digital value, and the third digital value, and update the second code based on a sum of the first code and the fifth code; and
the second circuit is configured to calibrate the gain of the first digital value based on the first code, calibrate the gain of the second digital value based on the second code, and calibrate a gain of the third digital value based on the fifth code.
4. The semiconductor integrated circuit according to claim 2 , wherein
the third circuit is configured to update the third code and a sixth code based on the first digital value, the second digital value, and the third digital value, and update the fourth code based on a sum of the third code and the sixth code; and
the fourth circuit is configured to calibrate the phase of the first clock signal based on the third code, calibrate the phase of the second clock signal based on the fourth code, and calibrate a phase of the third clock signal based on the sixth code.
5. The semiconductor integrated circuit according to claim 1 , wherein
the first circuit is configured to update the second code based on the first code in a case where a condition is satisfied, and stop updating the second code in a case where the condition is not satisfied.
6. The semiconductor integrated circuit according to claim 5 , wherein
the condition includes that an update amount of the first code is less than or equal to a threshold value.
7. The semiconductor integrated circuit according to claim 1 , wherein
the third circuit is configured to update the fourth code based on the third code in a case where a condition is satisfied, and stop updating the fourth code in a case where the condition is not satisfied.
8. The semiconductor integrated circuit according to claim 7 , wherein
the condition includes that an update amount of the third code is less than or equal to a threshold value.
9. A receiver device comprising:
a semiconductor integrated circuit according to claim 1 ; and
a control circuit configured to control processing of a signal output from the semiconductor integrated circuit.
10. The receiver device according to claim 9 , wherein
the semiconductor integrated circuit further comprises
a third converter configured to sample the analog signal and convert the sampled analog signal to a third digital value based on a third clock signal shifted a second phase from the first clock signal, and
the adjustment circuit is configured to adjust at least one of a gain of each of the first digital value, the second digital value, and the third digital value and a phase of each of the first clock signal, the second clock signal, and the third clock signal based on the first digital value, the second digital value, and the third digital value.
11. The receiver device according to claim 10 , wherein
the first circuit is configured to update the first code and a fifth code based on the first digital value, the second digital value, and the third digital value, and update the second code based on a sum of the first code and the fifth code; and
the second circuit is configured to calibrate the gain of the first digital value based on the first code, calibrate the gain of the second digital value based on the second code, and calibrate a gain of the third digital value based on the fifth code.
12. The receiver device according to claim 10 , wherein
the third circuit is configured to update the third code and a sixth code based on the first digital value, the second digital value, and the third digital value, and update the fourth code based on a sum of the third code and the sixth code; and
the fourth circuit is configured to calibrate the phase of the first clock signal based on the third code, calibrate the phase of the second clock signal based on the fourth code, and calibrate a phase of the third clock signal based on the sixth code.
13. The receiver device according to claim 9 , wherein
the first circuit is configured to update the second code based on the first code in a case where a condition is satisfied, and stop updating the second code in a case where the condition is not satisfied.
14. The receiver device according to claim 13 , wherein
the condition includes that an update amount of the first code is less than or equal to a threshold value.
15. The receiver device according to claim 9 , wherein
the third circuit is configured to update the fourth code based on the third code in a case where a condition is satisfied, and stop updating the fourth code in a case where the condition is not satisfied.
16. The receiver device according to claim 15 , wherein
the condition includes that an update amount of the third code is less than or equal to a threshold value.
17. A reception method comprising:
sampling an analog signal and converting the sampled analog signal to a first digital value based on a first clock signal;
sampling the analog signal and converting the sampled analog signal to a second digital value based on a second clock signal shifted a first phase from the first clock signal; and
adjusting at least one of a gain of each of the first digital value and the second digital value and a phase of each of the first clock signal and the second clock signal based on the first digital value and the second digital value, wherein
the adjusting includes:
updating a first code based on the first digital value and the second digital value, and updating a second code based on the first code; and
calibrating a gain of the first digital value based on the first code, and calibrating a gain of the second digital value based on the second code,
or
updating a third code based on the first digital value and the second digital value, and updating a fourth code based on the third code; and
calibrating a phase of the first clock signal based on the third code, and calibrating a phase of the second clock signal based on the fourth code.
18. The reception method according to claim 17 , wherein
the updating the second code includes updating the second code based on the first code in a case where a condition is satisfied, and stopping updating the second code in a case where the condition is not satisfied.
19. The reception method according to claim 15 , wherein
the updating the fourth code includes updating the fourth code based on the third code in a case where a condition is satisfied, and stopping updating the fourth code in a case where the condition is not satisfied.
20. The reception method according to claim 17 , further comprising:
sampling the analog signal and converting the sampled analog signal to a third digital value based on a third clock signal shifted a second phase from the first clock signal, wherein
the adjusting includes adjusting at least one of a gain of each of the first digital value, the second digital value, and the third digital value and a phase of each of the first clock signal, the second clock signal, and the third clock signal based on the first digital value, the second digital value, and the third digital value.