Compact static random-access memory structure

1. A static random-access memory (SRAM) structure comprising:

a first source/drain (S/D) feature and a second S/D feature formed in an interlayer dielectric layer (ILD) of a bit cell region of the SRAM structure, wherein the first S/D feature and the second S/D feature are of a same type;

a frontside via electrically connecting to the first S/D feature;

a first backside via electrically connecting to the second S/D feature; and

a third S/D feature formed in the ILD, wherein the third S/D feature is of a type different than the type of the first and the second S/D features.

2. The SRAM structure of claim 1 , further comprising:

a second backside via electrically connecting to the third S/D feature.

3. The SRAM structure of claim 2 , wherein the first S/D feature electrically connects to a drain voltage (VD), the second S/D feature electrically connects to a negative supply voltage (Vss), and the third S/D feature electrically connects to a positive supply voltage (Vdd).

4. The SRAM structure of claim 2 , wherein the first and second S/D features are N-type S/D features, and the third S/D feature is a P-type S/D feature.

5. The SRAM structure of claim 1 , further comprising

a S/D contact formed between the first S/D feature and the frontside via.

6. The SRAM structure of claim 1 , further comprising

semiconductor fins formed along sidewalls of the first and second S/D features; and

gate structures formed over the semiconductor fins.

7. The SRAM structure of claim 1 , further comprising an edge region free of a tap cell.

8. A semiconductor structure comprising:

a first source/drain (S/D) feature and a second S/D feature formed in a cell region of the semiconductor structure, wherein the first S/D feature and the second S/D feature are of different types and disposed over a first dielectric layer;

a second dielectric layer over the first S/D feature, the second S/D feature, and the first dielectric layer;

a first backside via extending through the first dielectric layer to electrically connect to the first S/D feature; and

a second backside via electrically connecting to the second S/D feature,

wherein the second dielectric layer interfaces and surrounds the first S/D feature and the second S/D feature.

9. The semiconductor structure of claim 8 , further comprising an edge region free of a tap cell.

10. The semiconductor structure of claim 9 , wherein a width of the edge region is equal or less than 4 critical poly pitches (CPP).

11. The semiconductor structure of claim 8 , further comprising:

a third S/D feature formed in the cell region of the semiconductor structure, wherein the third S/D feature is of the same type as the first S/D feature;

a S/D contact formed over the third S/D feature; and

a frontside via formed over the S/D contact and electrically connecting to the third S/D feature.

12. The semiconductor structure of claim 11 , wherein the first S/D feature and the third S/D feature are N-type S/D features and the second S/D feature is a P-type S/D feature.

13. The semiconductor structure of claim 12 , wherein the first S/D feature electrically connects to a negative supply voltage (Vss), the second S/D feature electrically connects to a positive supply voltage (Vdd), and the third S/D feature electrically connects to a drain voltage (VD).

14. The semiconductor structure claim 11 , further comprising:

semiconductor fins formed along sidewalls of the first, second, and third S/D features; and

gate structures formed over the semiconductor fins and electrically connecting to a gate voltage (VG).

15. A semiconductor structure, comprising:

a first dielectric layer;

a first rail and a second rail disposed in the first dielectric layer and spaced apart from one another;

a second dielectric layer disposed over the first dielectric layer, the first rail and the second rail;

a first backside via extending through the second dielectric layer to contact the first rail;

a second backside via extending through the second dielectric layer to contact the second rail;

a third dielectric layer disposed over the second dielectric layer;

a first epitaxial feature disposed in the third dielectric layer and in contact with a top surface of the first backside via;

a second epitaxial feature disposed in the third dielectric layer and in contact with a top surface of the second backside via;

a first frontside contact disposed over and in contact with the first epitaxial feature; and

a second frontside contact disposed over and in contact with the second epitaxial feature.

16. The semiconductor structure of claim 15 ,

wherein the first epitaxial feature comprises silicon (Si) and an n-type dopant,

wherein the second epitaxial feature comprises silicon germanium (SiGe) and a p-type dopant.

17. The semiconductor structure of claim 16 ,

wherein the first rail is coupled to a negative supply voltage (Vss),

wherein the second rail is coupled to a positive supply voltage (Vdd).

18. The semiconductor structure of claim 15 , wherein the first frontside contact and the second frontside contact are disposed in the third dielectric layer.

19. The semiconductor structure of claim 15 ,

wherein the first epitaxial feature and the second epitaxial feature are spaced apart from one another along a direction,

wherein a width of the first epitaxial feature along the direction and greater than a width of the second epitaxial feature along the direction.

20. The semiconductor structure of claim 15 , further comprising:

a third epitaxial feature disposed in the third dielectric layer and spaced apart from the second epitaxial feature,

wherein the third epitaxial feature is disposed on the second dielectric layer.