Semiconductor devices and data storage systems including the same
A semiconductor device includes a semiconductor structure that includes a substrate having a first region and a second region, gate electrodes stacked and spaced apart from each other in a first direction, extend at different lengths in a second direction on the second region, and include pad regions, interlayer insulating layers alternately stacked with the gate electrodes, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, contact plugs penetrating the pad regions and extending in the first direction on the second region, and contact insulating layers between the gate electrodes and between ones of the contact plugs below the pad regions. The pad regions and the contact insulating layers protrude from the interlayer insulating layers toward the contact plugs in a horizontal direction.
1. A semiconductor device, comprising:
a first semiconductor structure comprising a first substrate, circuit devices on the first substrate, and circuit interconnection lines electrically connected to the circuit devices; and
a second semiconductor structure on the first semiconductor structure,
wherein the second semiconductor structure comprises:
a second substrate having a first region and a second region;
gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, and extend at different lengths in a second direction on the second region, and comprising pad regions having upper surfaces exposed on the second region;
interlayer insulating layers alternately stacked with the gate electrodes;
channel structures on the first region which penetrate the gate electrodes and extend in the first direction, wherein each of the channel structures comprises a channel layer;
contact plugs that are connected to the pad regions of the gate electrodes, extend in the first direction, and penetrate the pad regions; and
contact insulating layers below the pad regions and respectively surrounding the contact plugs,
wherein the pad regions of the gate electrodes have a first thickness and other regions of the gate electrodes have a second thickness less than the first thickness, and
wherein the contact plugs contact portions of upper surfaces, side surfaces, and lower surfaces of respective ones of the pad regions.
2. The semiconductor device of claim 1 , wherein the pad regions and the contact insulating layers protrude from the interlayer insulating layers toward the contact plugs.
3. The semiconductor device of claim 2 , wherein a first length of a respective one of the pad regions protruding from the interlayer insulating layers is substantially same as a second length of a respective one of the contact insulating layers protruding from a respective one of the interlayer insulating layers.
4. The semiconductor device of claim 1 , wherein the contact plugs contact portions of upper surfaces, side surfaces, and lower surfaces of the contact insulating layers.
5. The semiconductor device of claim 1 , wherein the contact insulating layers surrounding each of the contact plugs are spaced apart from each other in the first direction.
6. The semiconductor device of claim 1 , wherein the contact insulating layers are spaced apart from each other and are between adjacent ones of the contact plugs.
7. The semiconductor device of claim 1 , wherein the contact insulating layers comprise a material different from a material of the interlayer insulating layers.
8. The semiconductor device of claim 7 , wherein the contact insulating layers comprise silicon nitride.
9. The semiconductor device of claim 1 ,
wherein each of the pad regions has a first pad portion including a region overlapping the contact insulating layers in the first direction, and a second pad portion surrounding the first pad portion, and
wherein the first pad portion and the second pad portion have different thicknesses.
10. The semiconductor device of claim 9 ,
wherein the second semiconductor structure further comprises gate dielectric layers extending along external surfaces of the gate electrodes that are parallel to the second substrate, and
wherein the gate dielectric layers are on upper and lower surfaces of the second pad portion in each of the pad regions, and do not extend to upper and lower surfaces of the first pad portion.
11. The semiconductor device of claim 1 ,
wherein the second semiconductor structure further comprises gate dielectric layers extending along external surfaces of the gate electrodes that are parallel to the second substrate, and
wherein side surfaces of the gate electrodes are in contact with the contact insulating layers without the gate dielectric layers interposed therebetween below the pad regions.
12. The semiconductor device of claim 1 , wherein the second semiconductor structure further comprises:
sacrificial insulating layers in contact with the gate electrodes and alternately stacked with the interlayer insulating layers in a third region in which the second substrate is not disposed; and
a through-via that penetrates the sacrificial insulating layers and the interlayer insulating layers, extends into the first semiconductor structure, and comprises a same material as a material of the contact plugs.
13. The semiconductor device of claim 12 , wherein the sacrificial insulating layers protrude from the interlayer insulating layers toward the through-via.
14. The semiconductor device of claim 1 , wherein the contact plugs extend into the first semiconductor structure.
15. The semiconductor device of claim 1 ,
wherein the second semiconductor structure further comprises a substrate insulating layer that penetrates the second substrate, and
wherein lower ends of the contact plugs extend into the substrate insulating layer.
16. The semiconductor device of claim 1 , wherein the second semiconductor structure further comprises:
a first horizontal conductive layer below the gate electrodes on the first region;
a horizontal insulating layer below the gate electrodes on the second region; and
a second horizontal conductive layer on the first horizontal conductive layer and the horizontal insulating layer.
17. A semiconductor device, comprising:
a substrate having a first region and a second region;
gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, wherein the gate electrodes comprise pad regions on the second region, and wherein ones of the gate electrode are different lengths from one another and extend in a second direction on the second region;
interlayer insulating layers alternately stacked with the gate electrodes;
channel structures on the first region that penetrate the gate electrodes and extend in the first direction, wherein each of the channel structures comprises a channel layer;
contact plugs which are on the second region and penetrate the pad regions and extend in the first direction; and
contact insulating layers below the pad regions that are interposed between the gate electrodes and ones of the contact plugs,
wherein the pad regions and the contact insulating layers protrude from the interlayer insulating layers toward the contact plugs in a horizontal direction.
18. The semiconductor device of claim 17 , wherein the contact plugs contact portions of upper surfaces, side surfaces, and lower surfaces of the pad regions.
19. The semiconductor device of claim 17 , wherein the contact plugs have a first diameter on upper surfaces of the pad regions and a second diameter equal to or less than the first diameter below the pad regions.
20. A data storage system, comprising:
a semiconductor storage device comprising a substrate having a first region and a second region, circuit devices on one side of the substrate, and input/output pads electrically connected to the circuit devices; and
a controller electrically connected to the semiconductor storage device through one or more of the input/output pads and configured to control the semiconductor storage device,
wherein the semiconductor storage device further comprises:
gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate extend at different lengths in a second direction on the second region, and comprise pad regions on the second region;
interlayer insulating layers alternately stacked with the gate electrodes;
channel structures on the first region that penetrate the gate electrodes and extend in the first direction, wherein each of the channel structures comprises a channel layer;
contact plugs that penetrate the pad regions and extend in the first direction on the second region; and
contact insulating layers interposed between the gate electrodes and ones of the contact plugs below the pad regions,
wherein the contact plugs contact portions of upper surfaces, side surfaces, and lower surfaces of the pad regions.