IP Library Granted Patent US 12,258,264
Granted Patent B2
US 12,258,264 · App. 17/805,436 · Granted Mar 25, 2025

Microelectromechanical system (MEMS) interconnect including spring body with at least two spring arms micromachined from silicon substrate

Inventors: Muir Kumph (Croton on Hudson, NY); Vivekananda P. Adiga (Ossining, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
B81B7/0006B81C1/00626H10N60/10B81B2207/015
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Quick Facts
Patent No.
US 12,258,264
App. No.
17/805,436
Granted
Mar 25, 2025
Kind
B2
Abstract

A microelectromechanical system (MEMS) device and method of fabrication are provided. The MEMS devices includes a silicon substrate. The silicon substrate includes a top surface. An interconnect is machined from the silicon substrate. The interconnect includes at a spring body that has least two spring arms. Each spring arm includes a first end distal from a center of the interconnect, a second end proximate the center of the interconnect, and a single turn of a constant curvature. Each spring arm is configured to move rotationally in a plane parallel to the top surface of the silicon substrate.

Claims (40)

1. A microelectromechanical system (MEMS) device, comprising:

a silicon substrate having a top surface;

an interconnect machined from the silicon substrate, wherein:

the interconnect includes a spring body,

the spring body includes two or more spring arms, wherein each spring arm includes:

a first end distal from a center of the interconnect;

a second end proximate the center of the interconnect; and

one or more silicon bumps on the center of the interconnect configured to make vertical physical contact with a connection point on another device, wherein the spring body is configured to provide vertical leeway in a direction of the physical contact.

2. The device of claim 1 , wherein the one or more silicon bumps are signal pedestals including a metallic surface for conducting an electrical signal.

3. The device of claim 2 , wherein the one or more signal pedestals include at least one ground pedestal.

4. The device of claim 1 , further comprising two or more landing pedestals on the silicon substrate positioned distally from the center of the interconnect.

5. The device of claim 4 , wherein the two or more landing pedestals are positioned adjacent corners of the silicon substrate.

6. The device of claim 1 , wherein the spring body is configured to move rotationally in a plane parallel to the top surface of the silicon substrate.

7. The device of claim 1 , wherein each distal end of each spring arm includes a second width that is wider than the constant width.

8. The device of claim 1 , further comprising a flange connecting the second proximate end to the center of the interconnect.

9. The device of claim 1 , wherein the first distal end of a first spring arm is on an opposite side of the silicon substrate from the first distal end of a second spring arm.

10. The device of claim 1 , wherein each spring arm is configured to spiral from the first distal end to the second proximate end.

11. A quantum computing device, comprising:

a transmon qubit circuit; and

a microelectromechanical system (MEMS) device, including:

a silicon substrate having a top surface;

an interconnect machined from the silicon substrate, wherein the interconnect includes a spring body,

the spring body includes two or more spring arms, wherein each spring arm includes:

a first end distal from a center of the interconnect;

a second end proximate the center of the interconnect; and

one or more silicon bumps on the center of the interconnect configured to make vertical physical contact with a connection point on another device, wherein the spring body is configured to provide vertical leeway in a direction of the physical contact.

12. The device of claim 11 , wherein the one or more silicon bumps are signal pedestals including a metallic surface for conducting an electrical signal.

13. The device of claim 12 , wherein the one or more signal pedestals include at least one ground pedestal.

14. The device of claim 11 , further comprising two or more landing pedestals on the silicon substrate positioned distally from the center of the interconnect.

15. The device of claim 14 , wherein the two or more landing pedestals are positioned adjacent corners of the silicon substrate.

16. The device of claim 11 , wherein the spring body is configured to move rotationally in a plane parallel to the top surface of the silicon substrate.

17. The device of claim 11 , wherein each spring arm is configured to spiral from the first distal end to the second proximate end.

18. A method of manufacturing a microelectromechanical system (MEMS) device, comprising:

controllably removing silicon from a silicon substrate, wherein one or more silicon features remain on the silicon substrate;

masking the silicon substrate and the one or more silicon features; and

selectively removing silicon from the silicon substrate based on a mask pattern defined by the masking step, wherein:

the mask pattern defines an interconnect including a spring body wherein the spring body includes at least two spring arms; and

each spring arm includes a first end distal from a center of the interconnect, a second end proximate the center of the interconnect, and one or more silicon bumps on the center of the interconnect configured to make vertical physical contact with a connection point on another device, wherein the spring body is configured to provide vertical leeway in a direction of the physical contact.

19. The method of claim 18 , wherein the one or more silicon features include a signal pedestal, a ground pedestal, or a landing pedestal.

20. The semiconductor package of claim 19 , wherein two or more of the landing pedestals on the silicon substrate are positioned distally from the center of the interconnect adjacent corners of the silicon substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2022
From: KUMPH, MUIR; ADIGA, VIVEKANANDA P.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 060102/0682 →
Continuity (1)
Related Publication 20230391609A1 · Dec 7, 2023
References Cited (15)
US 5973394A · Slocum et al. · 1999 [cited by applicant]
US 6250933B1 · Khoury et al. · 2001 [cited by applicant]
US 6262463B1 · Miu et al. · 2001 [cited by applicant]
US 6556737B1 · Miu et al. · 2003 [cited by applicant]
US 9187313B2 · Eskridge et al. · 2015 [cited by applicant]
US 10319896B2 · Falcon et al. · 2019 [cited by applicant]
US 10734696B2 · El Bouayadi et al. · 2020 [cited by applicant]
US 20130341735A1 · Eskridge · 2013 [cited by examiner]
US 20170213143A1 · Chow et al. · 2017 [cited by applicant]
US 20210005353A1 · Van Dyke · 2021 [cited by applicant]
US 20210343785A1 · Nakamura et al. · 2021 [cited by applicant]
TW 202119658B · 2020 [cited by applicant]
Spanier, G. et al., “Platform for Temporary Testing of Hybrid Microsystems at High Frequencies”, Journal of Microelectromechanical Systems (2007), vol. 16:6, pp. 1367-1377. [cited by applicant]
Rosenberg, D. et al., “3D Integration and Packaging for Solid-State Qubits”, ArXiv:1906.11146v2 (2019). 22 pgs. [cited by applicant]
International Search Report and Written Opinion issued Sep. 20, 2023 is related International Patent Application No. PCT/EP2023/064777, 11 pgs. [cited by applicant]