Hyperdimensional computing device
A hyperdimensional computing device includes a non-volatile memory cell array and a first operation circuit. The non-volatile memory cell array is coupled to a plurality of first word lines. The non-volatile memory cell array has a plurality of memory cell groups, a plurality of first memory cells of each of the memory cell groups are coupled to a same first word line of the first word lines, and the memory cell groups respectively store a plurality of data vectors. The first operation circuit receives at least one of the data vectors through bit lines and generates a bundled data vector according to the at least one of the data vectors.
1. A hyperdimensional computing device, comprising:
a non-volatile memory cell array, coupled to a plurality of first word lines, the memory cell array having a plurality of first memory cell groups, a plurality of first memory cells of each of the first memory cell groups being coupled to a same first word line of the first word lines, the first memory cell groups respectively storing a plurality of data vectors; and
a first operation circuit, coupled to a plurality of first bit lines of the non-volatile memory cell array, receiving at least one of the data vectors through the bit lines, and generating a bundled data vector according to the at least one of the data vectors,
wherein each of the data vectors is an n-gram vector, and the data vectors comprise all permutations and combinations of a plurality of characters.
2. The hyperdimensional computing device according to claim 1 , further comprising an encoder generating the n-gram vectors and respectively storing the n-gram vectors into the first memory cell groups.
3. The hyperdimensional computing device according to claim 1 , further comprising:
a word line driver, turning on a plurality of selected word lines of the first word lines according to input data.
4. The hyperdimensional computing device according to claim 3 , wherein the word line driver turns on each of the selected word lines one by one.
5. The hyperdimensional computing device according to claim 4 , wherein the operation circuit is a counter.
6. The hyperdimensional computing device according to claim 3 , wherein the word line driver synchronously turns on the selected word lines.
7. The hyperdimensional computing device according to claim 6 , wherein the operation circuit is a sensing amplifier.
8. A hyperdimensional computing device, comprising:
a non-volatile memory cell array, coupled to a plurality of first word lines, the memory cell array having a plurality of first memory cell groups, a plurality of first memory cells of each of the first memory cell groups being coupled to a same first word line of the first word lines, the first memory cell groups respectively storing a plurality of data vectors; and
a first operation circuit, coupled to a plurality of first bit lines of the non-volatile memory cell array, receiving at least one of the data vectors through the bit lines, and generating a bundled data vector according to the at least one of the data vectors, wherein the data vectors respectively comprise a plurality of possible component information and a plurality of position information corresponding to a graphic image.
9. The hyperdimensional computing device according to claim 8 , wherein the operation circuit generates the bundled data vector according to a plurality of selected component information and the position information respectively corresponding to the selected component information.
10. The hyperdimensional computing device according to claim 8 , further comprising:
an associative memory array, coupled to the operation circuit and configured to store a plurality of classification vectors, the associative memory array having a plurality of second memory cell groups, a plurality of second memory cells of each of the second memory cell groups being respectively coupled to a plurality of second word lines, the second memory cell groups being respectively coupled to a plurality of second bit lines, wherein the associative memory array receives the bundled data vector and performs an in-memory-searching operation according to the bundled data vector; and
a second operation circuit, coupled to the associative memory to generate an optimal similar result according to the in-memory-searching operation.
11. The hyperdimensional computing device according to claim 10 , wherein the second operation circuit generates the optimal similar result according to a current value of each of the second word lines.
12. The hyperdimensional computing device according to claim 11 , wherein the second operation circuit generates the optimal similar result according to one of the second word lines having a maximum current value.
13. The hyperdimensional computing device according to claim 10 , wherein the associative memory array is a NAND flash memory or a NOR flash memory.
14. The hyperdimensional computing device according to claim 1 , wherein the non-volatile memory cell array is a NAND flash memory or a NOR flash memory.