IP Library › Granted Patent US 12,261,082
Granted Patent B2
US 12,261,082 · App. 17/577,707 · Granted Mar 25, 2025

Semiconductor devices with a nitrided capping layer

Inventors: Po-Chin Chang (Taichung, TW); Lin-Yu Huang (Hsinchu, TW); Shuen-Shin Liang (Hsinchu, TW); Sheng-Tsung Wang (Hsinchu, TW); Cheng-Chi Chuang (New Taipei, TW); Chia-Hung Chu (Taipei, TW); Tzu Pei Chen (Hsinchu, TW); Yuting Cheng (Hsinchu, TW); Sung-Li Wang (Zhubei, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L21/76849H01L21/76805H01L21/7684H01L21/76846H01L21/76871H01L21/76895H01L23/535
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,261,082
App. No.
17/577,707
Granted
Mar 25, 2025
Kind
B2
Abstract

The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.

Claims (40)

1. A method, comprising:

forming a first conductive structure in a first dielectric layer on a substrate;

depositing a second dielectric layer on the first conductive structure and the first dielectric layer;

forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer;

forming a nitrided layer by performing a nitridation treatment to a top portion of the exposed first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer; and

forming a second conductive structure in the opening, wherein the second conductive structure is in contact with the nitrided layer.

2. The method of claim 1 , wherein forming the nitrided layer comprises performing a nitridation process using nitrogen (N 2 ) and ammonia (NH 3 ) with a gas flow rate between about 5 sccm and about 1000 sccm.

3. The method of claim 1 , wherein forming the nitrided layer comprises performing a nitrogen implantation process using N 2 with an implantation dose greater than about 1×10 15 atoms/cm 2 .

4. The method of claim 1 , wherein forming the nitrided layer comprises increasing a volume of the top portion of the first conductive structure between about 1.1 times and about 1.6 times.

5. The method of claim 1 , wherein forming the nitrided layer comprises reducing a conductivity of the top portion of the first conductive structure to between about 1×10 3 S/cm and about 1×10 6 S/cm.

6. The method of claim 1 , wherein forming the nitrided layer on the top portion of the portion of the first dielectric layer comprises replacing oxygen (O) atoms in the top portion of the portion of the first dielectric layer with nitrogen (N) atoms.

7. The method of claim 1 , wherein forming the nitrided layer comprises forming the nitrided layer with a nitrogen concentration initially increasing and then exponentially decreasing from a top surface of the nitrided layer to a bottom surface of the nitrided layer.

8. The method of claim 1 , further comprising forming a transistor structure on the substrate, wherein the first conductive structure is in contact with a gate conductive structure, a gate metal fill layer, and a source/drain (S/D) conductive structure of the transistor structure.

9. The method of claim 1 , wherein forming the second conductive structure comprises:

depositing a seed layer in the opening; and

polishing the second conductive structure, the seed layer, and the nitrided layer in the top portion of the second dielectric layer.

10. The method of claim 1 , wherein forming the second conductive structure comprises depositing, in the opening, a barrier layer with a thickness between about 0.2 nm and about 2 nm.

11. A method, comprising:

forming a transistor structure on a substrate;

forming a metal via in a first dielectric layer disposed on the transistor structure;

forming a nitrided layer including a nitrided metal layer and a nitrided dielectric layer on a top portion of the metal via and a top portion of the first dielectric layer, respectively;

depositing a second dielectric layer on the nitrided layer;

forming an opening in the second dielectric layer to expose the nitrided metal layer; and

forming a metal line in the opening, wherein the metal line is in contact with the nitrided metal layer.

12. The method of claim 11 , wherein forming the nitrided layer comprises performing a nitridation process using nitrogen (N 2 ) and ammonia (NH 3 ) with a gas flow rate between about 5 sccm and about 1000 sccm.

13. The method of claim 11 , wherein forming the nitrided layer comprises performing a nitrogen implantation process using N 2 with an implantation dose greater than about 1×10 15 atoms/cm 2 .

14. The method of claim 11 , wherein forming the nitrided layer comprises increasing a volume of the top portion of the metal via between about 1.1 times and about 1.6 times.

15. The method of claim 11 , wherein forming the nitrided layer on the top portion of the first dielectric layer comprises replacing oxygen (O) atoms in the top portion of the first dielectric layer with nitrogen (N) atoms.

16. The method of claim 11 , wherein forming the metal line comprises:

depositing, in the opening, one or more barrier layers with a thickness between about 0.2 nm and about 2 nm;

depositing a seed layer on the one or more barrier layers; and

polishing the metal line, the seed layer, and the one or more barrier layers.

17. A method, comprising:

depositing a dielectric layer on a substrate;

forming a metal line opening in the dielectric layer to expose a conductive via contact;

nitriding a top portion of the exposed conductive via contact, a dielectric sidewall of the metal line opening, and a top portion of the dielectric layer; and

forming a metal line in the metal line opening.

18. The method of claim 17 , wherein nitriding comprises performing a nitridation process using nitrogen (N 2 ) and ammonia (NH 3 ) with a gas flow rate between about 5 sccm and about 1000 sccm.

19. The method of claim 17 , wherein nitriding comprises performing a nitrogen implantation process using N 2 with an implantation dose greater than about 1×10 15 atoms/cm 2 .

20. The method of claim 17 , wherein nitriding comprises increasing a volume of the top portion of the conductive via contact between about 1.1 times and about 1.6 times.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2022
From: CHANG, PO-CHIN; HUANG, LIN-YU; LIANG, SHUEN-SHIN; WANG, SHENG-TSUNG; CHUANG, CHENG-CHI; CHU, CHIA-HUNG; CHEN, TZU PEI; CHENG, YUTING; WANG, SUNG-LI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 059143/0620 →
Continuity (2)
Provisional Application 63224897 · Jul 23, 2021
Related Publication 20230029002A1 · Jan 26, 2023
References Cited (9)
US 6140024A · Misium · 2000 [cited by examiner]
US 6174823B1 · Dobson · 2001 [cited by examiner]
US 6358849B1 · Havemann · 2002 [cited by examiner]
US 7727882B1 · Wu · 2010 [cited by examiner]
US 8962479B2 · Yang · 2015 [cited by examiner]
US 9006064B2 · Chudzik · 2015 [cited by examiner]
US 10115670B2 · Edelstein · 2018 [cited by examiner]
US 20060183327A1 · Moon · 2006 [cited by examiner]
US 20210202310A1 · Hsieh · 2021 [cited by examiner]