IP Library › Granted Patent US 12,261,221
Granted Patent B2
US 12,261,221 · App. 17/686,215 · Granted Mar 25, 2025

Transistor, semiconductor memory device, and manufacturing method for transistor

Inventors: Kiwamu Sakuma (Mie, JP); Taro Shiokawa (Aichi, JP); Keiko Sakuma (Mie, JP)
Assignee: KIOXIA CORPORATION
H01L29/78642H01L29/66969H01L29/7869H01L29/78696H10B12/30H10B41/35H10B43/35
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Quick Facts
Patent No.
US 12,261,221
App. No.
17/686,215
Granted
Mar 25, 2025
Kind
B2
Abstract

A transistor includes an upper electrode; a lower electrode; a gate electrode disposed between the upper electrode and the lower electrode; and a columnar portion penetrating the gate electrode and provided between the upper electrode and the lower electrode. The columnar portion includes a tubular gate insulating film and a semiconductor layer, the tubular gate insulating film disposed at a first distance away from the upper electrode and in contact with the gate electrode. The semiconductor layer is embedded in the tubular gate insulating film and between the gate insulating film and the upper electrode and in contact with the upper electrode.

Claims (19)

1. A transistor comprising:

an upper electrode;

a lower electrode;

a gate electrode disposed between the upper electrode and the lower electrode;

a columnar portion penetrating the gate electrode and disposed between the upper electrode and the lower electrode,

wherein the columnar portion includes a tubular gate insulating film and a semiconductor layer, the tubular gate insulating film disposed at a first distance away from the upper electrode and in contact with the gate electrode, the semiconductor layer embedded in the tubular gate insulating film and disposed between the tubular gate insulating film and the upper electrode and being in contact with the upper electrode; and

wherein at least a part of a side surface of a part of the semiconductor layer embedded between the tubular gate insulating film and the upper electrode is in contact with the upper electrode.

2. The transistor according to claim 1 , wherein the first distance is equal to or less than a film diameter of a part of the semiconductor layer embedded in the tubular gate insulating film.

3. The transistor according to claim 1 , wherein a film diameter of the part of the semiconductor layer embedded in the tubular gate insulating film, a film diameter of the part of the semiconductor layer embedded between the tubular gate insulating film and the upper electrode, and a radius of the columnar portion, have a relationship of T 2 a <T 2 b <T 3 where T 2 a is the film diameter of the part of the semiconductor layer embedded in the tubular gate insulating film, T 2 b is the film diameter of the part of the semiconductor layer embedded between the tubular gate insulating film and the upper electrode, and T 3 is the radius of the columnar portion.

4. The transistor according to claim 1 , wherein the semiconductor layer includes an oxide semiconductor.

5. The transistor according to claim 4 , wherein the semiconductor layer contains oxygen, indium, gallium, and zinc.

6. The transistor according to claim 4 , wherein the semiconductor layer contains at least one of indium, zinc, or tin.

7. The transistor according to claim 1 , wherein the semiconductor layer includes a recess portion in a middle on an upper electrode side, wherein at least a part of the recess portion of the semiconductor layer comes into contact with the upper electrode.

8. The transistor according to claim 1 , wherein the columnar portion is tapered.

9. A semiconductor memory device comprising the transistor according to claim 1 .

10. The semiconductor memory device according to claim 9 , wherein the transistor includes a transistor of a NAND flash memory.

11. The semiconductor memory device according to claim 9 , wherein the transistor is a transistor of a dynamic random access memory (DRAM).

12. The transistor according to claim 1 , wherein the semiconductor layer includes a channel.

13. The transistor according to claim 8 , wherein a radius of the columnar portion decreases toward the lower electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2022
From: SAKUMA, KIWAMU; SHIOKAWA, TARO; SAKUMA, KEIKO
To: KIOXIA CORPORATION
Reel/Frame 060047/0330 →
Priority Claims (1)
JP 2021-153213 · Sep 21, 2021 · national
Continuity (1)
Related Publication 20230103593A1 · Apr 6, 2023
References Cited (22)
US 5616511A · Hirota · 1997 [cited by applicant]
US 5627390A · Maeda · 1997 [cited by examiner]
US 9502431B2 · Sakuma et al. · 2016 [cited by applicant]
US 9698272B1 · Ikeda · 2017 [cited by examiner]
US 9780170B2 · Ota et al. · 2017 [cited by applicant]
US 9818757B2 · Ikeda et al. · 2017 [cited by applicant]
US 20120280303A1 · Kiyotoshi · 2012 [cited by examiner]
US 20170040416A1 · Ota · 2017 [cited by examiner]
US 20190058008A1 · Yagishita et al. · 2019 [cited by applicant]
US 20190237581A1 · Saito · 2019 [cited by examiner]
US 20200135242A1 · Arai et al. · 2020 [cited by applicant]
US 20210036011A1 · Son et al. · 2021 [cited by applicant]
US 20230088455A1 · Shiokawa · 2023 [cited by examiner]
JP H01225147A · 1989 [cited by applicant]
JP H05029577A · 1993 [cited by applicant]
JP H05067730A · 1993 [cited by applicant]
JP H05175450A · 1993 [cited by applicant]
JP H05226609A · 1993 [cited by applicant]
JP H05259387A · 1993 [cited by applicant]
JP H06151753A · 1994 [cited by applicant]
JP H07045788A · 1995 [cited by applicant]
Shosuke Fujii et al., “Oxide-semiconductor Channel Transistor DRAM (OCTRAM) with 4F2 Architecture”, 70th International Electron Devices Meeting, Dec. 9, 2024, San Francisco, CA, U.S.A. (4 pages). [cited by applicant]
Cited By (2)
US 12,432,905 US 12,484,212