Amplifier with stacked transconducting cells in current mode combining
An amplifier with stacked transconducting cells in “current mode combining” is disclosed herein. In one or more embodiments, a method for operation of a high-voltage signal amplifier comprises inputting, into each transconducting cell of a plurality of transconducting cells, a direct current (DC) supply current (Idc), an alternating current (AC) radio frequency (RF) input current (I RF_IN ), and an RF input signal (RF IN ). The method further comprises outputting, by each of the transconducting cells of the plurality of transconducting cells, the DC supply current (Idc) and an AC RF output current (I RF_OUT ). In one or more embodiments, the transconducting cells are connected together in cascode for the DC supply current, and are connected together in cascade for the AC RF input and output currents.
1. A method for operation of a high-voltage signal amplifier, the method comprising:
inputting, into each transconducting cell of a plurality of transconducting cells, a direct current (DC) supply current (Idc), an alternating current (AC) radio frequency (RF) input current (I RF_IN ), and an RF input signal (RF IN ); and
outputting, by each of the plurality of transconducting cells of the plurality of transconducting cells, the DC supply current (Idc) and an AC RF output current (I RF_OUT ),
wherein the plurality of transconducting cells are connected together in cascode for the DC supply current, and are connected together in cascade for the AC RF input and output currents.
2. The method of claim 1 , wherein the method further comprises splitting a power supply voltage (Vdd) evenly amongst the plurality of transconducting cells to power the plurality of transconducting cells.
3. The method of claim 2 , wherein a DC supply voltage drop of Vdd/N, where N is a number of the plurality of transconducting cells, is across each of the plurality of transconducting cells.
4. The method of claim 1 , wherein the method further comprises providing, by an input signal source (Vin), the RF input signal (RF IN ) to an input matching network (M1).
5. The method of claim 4 , wherein the input matching network (M1) is a single-input single-output matching network.
6. The method of claim 4 , wherein the method further comprises transforming, by the input matching network (M1), the RF input signal (RF IN ) to provide a power match to an input of each of the plurality of transconducting cells.
7. The method of claim 1 , wherein the method further comprises inputting, the AC RF output current (I RF_OUT ) outputted from a last transconducting cell of the plurality transconducting cells, into an output matching network (M2) to deliver power to a load impedance (R L ).
8. The method of claim 7 , wherein the output matching network (M2) is a single-input single-output matching network.
9. The method of claim 1 , wherein each of the plurality of transconducting cells comprises a metal oxide silicon field effect transistor (MOSFET).
10. The method of claim 1 , wherein each of the plurality of transconducting cells comprises a bipolar junction transistor (BJT).
11. A high-voltage signal amplifier, the amplifier comprising:
a plurality of transconducting cells, each configured to receive a direct current (DC) supply current (Idc), an alternating current (AC) radio frequency (RF) input current (I RF_IN ), and an RF input signal (RF IN ); and each configured to output the DC supply current (Idc) and an AC RF output current (I RF_OUT ), and
wherein the plurality of transconducting cells are connected together in cascode for the DC supply current, and are connected together in cascade for the AC RF input and output currents.
12. The amplifier of claim 11 , wherein each of the plurality of transconducting cells is further configured to receive a supply voltage (Vdd), which is split evenly amongst the plurality of transconducting cells, to power the plurality of transconducting cells.
13. The amplifier of claim 12 , wherein a DC supply voltage drop of Vdd/N, where N is a number of the plurality of transconducting cells, is across each of the plurality of transconducting cells.
14. The amplifier of claim 11 , wherein the amplifier further comprises:
an input matching network (M1); and
an input signal source (Vin) to provide the RF input signal (RF IN ) to the input matching network (M1).
15. The amplifier of claim 14 , wherein the input matching network (M1) is a single-input single-output matching network.
16. The amplifier of claim 14 , wherein the input matching network (M1) is configured to transform the RF input signal (RF IN ) to provide a power match to an input of each of the plurality of transconducting cells.
17. The amplifier of claim 11 , wherein the amplifier further comprises an output matching network (M2) configured to receive the AC RF output current (I RF_OUT ) outputted from a last transconducting cell of the plurality transconducting cells to deliver power to a load impedance (R L ).
18. The amplifier of claim 17 , wherein the output matching network (M2) is a single-input single-output matching network.
19. The amplifier of claim 11 , wherein each of the plurality of transconducting cells comprises a metal oxide silicon field effect transistor (MOSFET).
20. The amplifier of claim 11 , wherein each of the plurality of transconducting cells comprises a bipolar junction transistor (BJT).
21. A method for operation of a high-voltage multi-stage signal amplifier, the method comprising:
inputting, into each transconducting cell of a plurality of transconducting cells of a first stage, a direct current (DC) supply current (Idc), an alternating current (AC) radio frequency (RF) input current (I RF_IN ), and an RF input signal (RF IN );
inputting, into each transconducting cell of a plurality of transconducting cells of a second stage, the DC supply current (Idc), the AC RF input current (I RF_IN ), and the RF input signal (RF IN );
outputting, by each of the transconducting cells of the plurality of transconducting cells of the first stage, the DC supply current (Idc) and an AC RF output current (I RF_OUT ); and
outputting, by each of the transconducting cells of the plurality of transconducting cells of the second stage, the DC supply current (Idc) and the AC RF output current (I RF_OUT ),
wherein the plurality of transconducting cells of the first stage are connected together in cascode for the DC supply current, and are connected together in cascade for the AC RF input and output currents,
wherein the plurality of transconducting cells of the second stage are connected together in cascode for the DC supply current, and are connected together in cascade for the AC RF input and output currents, and
wherein the first stage and the second stage are connected together in cascode for the DC supply current, and are connected together in cascade for the AC RF input and output currents.
22. The method of claim 21 , wherein the method further comprises splitting a power supply voltage (Vdd) evenly amongst the plurality of transconducting cells of the first stage and the second stage to power the plurality of transconducting cells of the first stage and the second stage.
23. The method of claim 21 , wherein a DC supply voltage drop of Vdd/N, where N is a number of the transconducting cells of the first stage and the second stage, is across each of the plurality of transconducting cells of the first stage and the second stage.
24. The method of claim 21 , wherein the method further comprises providing, by an input signal source (Vin), the RF input signal (RF IN ) to an input matching network (M1).
25. The method of claim 24 , wherein the input matching network (M1) is a single-input single-output matching network.
26. The method of claim 24 , wherein the method further comprises transforming, by the input matching network (M1), the RF input signal (RF IN ) to provide a power match to an input of each of the plurality of transconducting cells of the first stage.
27. The method of claim 21 , wherein the method further comprises inputting, the AC RF output current (I RF_OUT ) outputted from a last transconducting cell of the plurality transconducting cells of the first stage, into an inner stage matching network (M2) to deliver power to the plurality of transconducting cells of the second stage.
28. The method of claim 27 , wherein the inner stage matching network (M2) is a single-input single-output matching network.
29. The method of claim 21 , wherein the method further comprises inputting, the AC RF output current (I RF_OUT ) outputted from a last transconducting cell of the plurality transconducting cells of the second stage, into an output matching network (M3) to deliver power to a load (R L ).
30. The method of claim 29 , wherein the output matching network (M3) is a single-input single-output matching network.
31. A high-voltage multi-stage signal amplifier, the amplifier comprising:
a plurality of transconducting cells of a first stage, each configured to receive a direct current (DC) supply current (Idc), an alternating current (AC) radio frequency (RF) input current (I RF_IN ), and an RF input signal (RF IN ); and each configured to output the DC supply current (Idc) and an AC RF output current (I RF_OUT ),
wherein the plurality of transconducting cells of the first stage are connected together in cascode for the DC supply current, and are connected together in cascade for the AC RF input and output currents; and
a plurality of transconducting cells of a second stage, each configured to receive the DC supply current (Idc), the AC RF input current (I RF_IN ), and the RF input signal (RF IN ); and each configured to output the DC supply current (Idc) and the AC RF output current (I RF_OUT ),
wherein the plurality of transconducting cells of the second stage are connected together in cascode for the DC supply current, and are connected together in cascade for the AC RF input and output currents, and
wherein the first stage and the second stage are connected together in cascode for the DC supply current, and are connected together in cascade for the AC RF input and output currents.
32. The amplifier of claim 31 , wherein the each of the plurality of transconducting cells of the first stage and the second stage is configured to receive a supply voltage (Vdd), which is split evenly amongst the plurality of transconducting cells of the first stage and the second stage to power the plurality of transconducting cells of the first stage and the second stage.
33. The amplifier of claim 31 , wherein a DC supply voltage drop of Vdd/N, where N is a number of the transconducting cells of the first stage and the second stage, is across each of the plurality of transconducting cells of the first stage and the second stage.
34. The amplifier of claim 31 , wherein the amplifier further comprises:
an input matching network (M1); and
an input signal source (Vin) to provide the RF input signal (RF IN ) to the input matching network (M1).
35. The amplifier of claim 34 , wherein the input matching network (M1) is a single-input single-output matching network.
36. The amplifier of claim 34 , wherein the input matching network (M1) is further configured to transform the RF input signal (RF IN ) to provide a power match to an input of each of the plurality of transconducting cells of the first stage.
37. The amplifier of claim 31 , wherein the amplifier further comprises an inner stage matching network (M2) configured to receive the AC RF output current (I RF_OUT ), which is outputted from a last transconducting cell of the plurality transconducting cells of the first stage, to deliver power to the plurality of transconducting cells of the second stage.
38. The amplifier of claim 37 , wherein the inner stage matching network (M2) is a single-input single-output matching network.
39. The amplifier of claim 31 , wherein the amplifier further comprises an output matching network (M3) configured to receive the AC RF output current (I RF_OUT ), which is outputted from a last transconducting cell of the plurality transconducting cells of the second stage, to deliver power to a load (R L ).
40. The amplifier of claim 39 , wherein the output matching network (M3) is a single-input single-output matching network.