Amplifier peak detection
A peak detector for a power amplifier is provided that includes a threshold voltage detector configured to pulse a detection current in response to an amplified output signal from the amplifier exceeding a peak threshold. A plurality of such peak detectors may be integrated with a corresponding plurality of power amplifiers in a transmitter. Should any peak detector assert an alarm signal or more than a threshold number of alarm signals during a given period, a controller reduces a gain for the plurality of power amplifiers.
1. A peak detector, comprising:
a voltage divider configured to divide an amplifier output signal into a divided signal;
a threshold voltage detector configured to conduct a detection current in response to the divided signal being greater than a threshold voltage;
a current mirror configured to mirror the detection current into a mirrored current and configured to drive the mirrored current into a node; and
at least one inverter configured to invert a voltage of the node to produce a binary output signal,
wherein the threshold voltage detector comprises
a first transistor having a gate configured to be driven by the divided signal,
a source bias circuit configured to bias a source of the first transistor,
a gate bias circuit configured to bias a gate of the first transistor, and
a drain bias circuit configured to bias a drain of the first transistor,
wherein the source bias circuit comprises:
a first current source configured to drive a resistor with a first current to develop a source bias voltage at a terminal of the resistor,
a second transistor;
a second current source configured to drive a second current into a drain of the second transistor; and
a differential amplifier having a first input coupled to the terminal of the resistor, a second input coupled to the source of the first transistor; and an output coupled to a gate of the second transistor, wherein the differential amplifier and the second transistor are configured to form a feedback loop to bias the source of the first transistor with the source bias voltage.
2. The peak detector of claim 1 , further comprising:
a counter configured to count binary transitions in the binary output signal to form a count and configured to assert a peak detector alarm signal in response to the count exceeding a peak detection threshold count.
3. The peak detector of claim 2 , wherein the counter is a ripple counter.
4. The peak detector of claim 2 , further comprising:
a controller configured to command the amplifier to reduce a gain in response to an assertion of the peak detector alarm signal.
5. The peak detector of claim 1 , wherein the first transistor is an n-type-metal-oxide-semiconductor (NMOS) transistor, and the second transistor is a p-type-metal-oxide-semiconductor (PMOS) transistor.
6. The peak detector of claim 1 , wherein the first current source is a variable current source.
7. The peak detector of claim 1 , wherein the first transistor comprises an NMOS transistor configured to conduct the detection current, and wherein the current mirror comprises a diode-connected first PMOS transistor having a gate connected to a gate of a second PMOS transistor.
8. The peak detector of claim 7 , wherein a drain of the second PMOS transistor is coupled to the node.
9. The peak detector of claim 1 , wherein the at least one inverter comprises a pair of inverters.
10. A peak detector, comprising:
a voltage divider configured to divide an amplifier output signal into a divided signal;
a threshold voltage detector configured to conduct a detection current in response to the divided signal being greater than a threshold voltage;
a current mirror configured to mirror the detection current into a mirrored current and configured to drive the mirrored current into a node; and
at least one inverter configured to invert a voltage of the node to produce a binary output signal,
wherein the threshold voltage detector comprises
a first transistor having a gate configured to be driven by the divided signal,
a source bias circuit configured to bias a source of the first transistor,
a gate bias circuit configured to bias a gate of the first transistor, and
a drain bias circuit configured to bias a drain of the first transistor,
wherein the gate bias circuit comprises:
a first current source configured to drive a first resistor with a first current to develop a bias voltage at a terminal of the first resistor;
a second transistor;
a second current source configured to drive a second current into a drain of the second transistor; and
a differential amplifier having a first input coupled to the terminal of the first resistor, a second input coupled to the drain of the second transistor; and an output coupled to a gate of the second transistor, wherein the differential amplifier and the second transistor are configured to form a feedback loop to bias the gate of the first transistor with a gate bias voltage equal to the bias voltage at the terminal of the first resistor.
11. The peak detector of claim 10 , further comprising:
a counter configured to count binary transitions in the binary output signal to form a count and configured to assert a peak detector alarm signal in response to the count exceeding a peak detection threshold count.
12. The peak detector of claim 11 , wherein the counter is a ripple counter.
13. The peak detector of claim 11 , further comprising:
a controller configured to command the amplifier to reduce a gain in response to an assertion of the peak detector alarm signal.
14. The peak detector of claim 10 , wherein the gate bias circuit further comprises a second resistor coupled between the gate of the first transistor and the gate of the second transistor.
15. The peak detector of claim 10 , wherein the first transistor comprises an NMOS transistor configured to conduct the detection current, and wherein the current mirror comprises a diode-connected first PMOS transistor having a gate connected to a gate of a second PMOS transistor.
16. The peak detector of claim 15 , wherein a drain of the second PMOS transistor is coupled to the node.
17. The peak detector of claim 10 , wherein the at least one inverter comprises a pair of inverters.
18. A peak detector, comprising:
a voltage divider configured to divide an amplifier output signal into a divided signal;
a threshold voltage detector configured to conduct a detection current in response to the divided signal being greater than a threshold voltage;
a current mirror configured to mirror the detection current into a mirrored current and configured to drive the mirrored current into a node; and
at least one inverter configured to invert a voltage of the node to produce a binary output signal,
wherein the threshold voltage detector comprises
a first transistor having a gate configured to be driven by the divided signal,
a source bias circuit configured to bias a source of the first transistor,
a gate bias circuit configured to bias a gate of the first transistor, and
a drain bias circuit configured to bias a drain of the first transistor,
wherein the drain bias circuit comprises:
a first current source configured to drive a resistor with a first current to develop a drain bias voltage at a terminal of the resistor,
a second transistor having a source coupled to a drain of the first transistor;
a second current source configured to drive a second current into ground from the source of the second transistor; and
a differential amplifier having a first input coupled to the terminal of the resistor, a second input coupled to the drain of the first transistor; and an output coupled to a gate of the second transistor, wherein the differential amplifier and the second transistor are configured to form a feedback loop to bias the drain of the first transistor with the drain bias voltage.
19. The peak detector of claim 18 , further comprising:
a counter configured to count binary transitions in the binary output signal to form a count and configured to assert a peak detector alarm signal in response to the count exceeding a peak detection threshold count.
20. The peak detector of claim 19 , wherein the counter is a ripple counter.
21. The peak detector of claim 19 , further comprising:
a controller configured to command the amplifier to reduce a gain in response to an assertion of the peak detector alarm signal.
22. The peak detector of claim 18 , wherein the first transistor comprises an NMOS transistor configured to conduct the detection current, and wherein the current mirror comprises a diode-connected first PMOS transistor having a gate connected to a gate of a second PMOS transistor.
23. The peak detector of claim 22 , wherein a drain of the second PMOS transistor is coupled to the node.
24. The peak detector of claim 18 , wherein the at least one inverter comprises a pair of inverters.