Transistor device having a comb-shaped channel region to increase the effective gate width
A method of forming a comb-shaped transistor device is provided. The method includes forming a stack of alternating sacrificial spacer segments and channel segments on a substrate. The method further includes forming channel sidewalls on opposite sides of the stack of alternating sacrificial spacer segments and channel segments, and dividing the stack of alternating sacrificial spacer segments and channel segments into alternating sacrificial spacer slabs and channel slabs, wherein the channel slabs and channel sidewalls form a pair of comb-like structures. The method further includes trimming the sacrificial spacer slabs and channel slabs to form a nanosheet column of sacrificial plates and channel plates, and forming source/drains on opposite sides of the sacrificial plates and channel plates.
1. A field effect transistor device with a comb-like channel structure, comprising:
a first channel sidewall on an insulating layer, the first channel sidewall including a planar outer surface, the first channel sidewall connecting a source region to a drain region;
a plurality of first channel plates in physical and electrical contact with a sidewall surface of the first channel sidewall, wherein the first channel plates extends laterally from a side face of the first channel sidewall that is opposite the planar outer surface in a direction perpendicular to a direction separating the source region from the drain region, and the first channel sidewall extends above an uppermost first channel plate to provide an apex, the first channel sidewall contacting the insulating layer opposite the apex;
a gate dielectric layer on a portion of the plurality of channel plates and the channel sidewall; and
a conductive gate electrode on the gate dielectric layer.
2. The field effect transistor device of claim 1 , wherein the first channel sidewall has a thickness about equal to the thickness of each of the plurality of first channel plates.
3. The field effect transistor device of claim 2 , wherein the plurality of first channel plates each have a thickness of about 4 nanometers (nm) to about 12 nm.
4. The field effect transistor device of claim 2 , wherein the plurality of first channel plates and the first channel sidewall are silicon (Si).
5. The field effect transistor device of claim 2 , wherein the first channel sidewall and the plurality of first channel plates increase the channel width and increase the drive current capacity of the field effect transistor device.
6. The field effect transistor device of claim 1 , further comprising a second channel sidewall on the insulating layer, and a plurality of second channel plates in physical and electrical contact with the second channel sidewall, wherein the first channel plates and the second channel plates extend towards each other from the first channel sidewall and the second channel sidewall, respectively.
7. The field effect transistor device of claim 6 , wherein the conductive gate electrode fills in a space between the first channel plates and the second channel plates.
8. The field effect transistor device of claim 6 , wherein the gate dielectric layer is also on the second channel sidewall and the plurality of second channel plates.
9. A field effect transistor device with a comb-like channel structure, comprising:
a first channel sidewall on an insulating layer including a planar outer surface;
a plurality of first channel plates in physical and electrical contact with a sidewall surface of the first channel sidewall, wherein the first channel plates extends laterally from a side face of the first channel sidewall that is opposite the planar outer surface, and the first channel sidewall extends above an uppermost first channel plate to provide an apex, the first channel sidewall contacting the insulating layer opposite the apex;
a second channel sidewall on the substrate;
a plurality of second channel plates in physical and electrical contact with the second channel sidewall, wherein the second channel plates extend outward from a side face of the second channel sidewall, wherein the plurality of the second channel plates and the plurality of the first channel plates extend along a direction perpendicular from a dimension separating a source region from a drain region;
a gate dielectric layer on a portion of the surfaces of the plurality of the first channel plates and the first channel sidewall, and a portion of the surfaces of the plurality of the second channel plates and the second channel sidewall; and
a conductive gate electrode on the gate dielectric layer, wherein the conductive gate electrode fills in a space between the first channel plates and the second channel plates.
10. The field effect transistor device of claim 9 , wherein the plurality of first channel plates each have a thickness of about 4 nanometers (nm) to about 12 nm.
11. The field effect transistor device of claim 10 , wherein the plurality of first channel plates and the first channel sidewall are silicon (Si).
12. The field effect transistor device of claim 9 , further comprising a first pair of source/drains on opposite sides of the first channel plates and the first channel sidewall.
13. The field effect transistor device of claim 12 , further comprising a second pair of source/drains on opposite sides of the second channel plates and the second channel sidewall.
14. A field effect transistor device with a comb-like channel structure, comprising:
a first channel sidewall on an insulating layer, wherein the first channel sidewall including a planar outer surface;
a plurality of first channel plates in physical and electrical contact with a sidewall surface of the first channel sidewall, wherein the first channel plates extends laterally from a side face of the first channel sidewall that is opposite the planar outer surface, and the first channel sidewall extends above an uppermost first channel plate to provide an apex, the first channel sidewall contacting the insulating layer opposite the apex;
a second channel sidewall on the substrate;
a plurality of second channel plates in physical and electrical contact the second channel sidewall, wherein the second channel plates extend outward from a side face of the second channel sidewall;
a gate dielectric layer on a portion of the surfaces of the plurality of the first channel plates and the first channel sidewall, and a portion of the surfaces of the plurality of the second channel plates and the second channel sidewall;
a conductive gate electrode on the gate dielectric layer, wherein the conductive gate electrode fills in a space between the first channel plates and the second channel plates;
a first pair of source/drains on opposite sides of the plurality of first channel plates and the first channel sidewall, wherein the plurality of the first channel plates extend along a first direction perpendicular from a first dimension separating the first pair of source/drains; and
a second pair of source/drains on opposite sides of the plurality second channel plates and the second channel sidewall, wherein the plurality of the second channel plates extend along a second direction perpendicular from a second dimension separating the second pair of source/drains.
15. The field effect transistor device of claim 14 , wherein the first and second channel sidewalls each have a width in a range of about 4 nanometers (nm) to about 12 nm.
16. The field effect transistor device of claim 14 , further comprising inner spacers between the first pair of source/drains and the conductive gate electrode, and between the second pair of source/drains and the conductive gate electrode.
17. The field effect transistor device of claim 16 , wherein the plurality of first channel plates, the first channel sidewall, the plurality of second channel plates and the second channel sidewall are silicon (Si).
18. The field effect transistor device of claim 17 , wherein the gate dielectric layer is on the insulating layer.